Hy3313681373

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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

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Hy3313681373

  1. 1. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731368 | P a g eDesign and FPGA Prototyping of Embedded Ethernet ControllerN.Prathima*, K.HariKishore**, Dr.Fazal Noorbasha***,*(M.Tech VLSI Student, Department of ECE, KL University, Guntur, A.P, India)** (Assistant Professor, Department of ECE, KL University, Guntur, A.P, India)*** (Associate Professor, Department of ECE, KL University, Guntur, A.P, India)ABSTRACTPresently, the embedded system, whichwas composed of SOC, entered into people’s lifemore and more widely. We can see it frequentlywhether in the mobile phones, television,industrial control equipment or network devices.With the continuous expansion of network scaleand the increase of service, the embedded Internethas played an increasingly important role.Ethernet is the most widely used LANtechnology in the present day world. With theincreasing use of embedded systems, the need forincorporating Ethernet connectivity into theembedded systems is greatly felt. Therefore, thestudy of Ethernet communication on embeddedsystem is necessary. The embedded Ethernet iswidely applied, and its research is very important.In this paper a 10/100 Mbps embeddedethernet controller has been developed inVerilog-HDL, that can support two speeds(10/100Mbps), two modes (full/half duplex), andcan communicate with PHY through MII. TheEthernet controller designed conforms to thestandards of IEEE 802.3 communicationprotocol. The simulation has been done usingModelSim6.4SE. FPGA Prototyping was doneusing Xilinx EDK tool on Xilinx Virtex-5FX70TFPGA. The packet capture has been done usingWireshark tool.Keywords-LAN, Ethernet, OSI reference model,MII, CSMA/CD, EMAC, and Ethernet PHY.I. INTRODUCTIONIn todays business world, reliable andefficient access to information has become animportant asset in the quest to achieve a competitiveadvantage. File cabinets and mountains of papershave given way to computers that store and manageinformation electronically. Computer networkingtechnologies are the glue that binds these elementstogether. Networking allows one computer to sendinformation to and receive information from another.We can classify network technologies asbelonging to one of two basic groups. Local areanetwork (LAN) technologies connect many devicesthat are relatively close to each other, usually in thesame building. In comparison to WANs, LANs arefaster and more reliable, but improvements intechnology continue to blur the line of demarcation.Fiber optic cables have allowed LAN technologies toconnect devices tens of kilometres apart.Ethernet is a family of frame‐basedcomputer networking technologies for Local AreaNetwork (LAN). The name came from the physicalconcept of the ether. It defines a number of wiringand signalling standards for the Physical Layer of theOSI networking model as well as a commonaddressing format and Media Access Control at theData Link Layer. The combination of the twisted pairversions of Ethernet for connecting end systems tothe network, along with the fiber optic version is themost widespread wired LAN technology. Ethernethas been used from around 1980 to the present,largely replacing competing LAN standards such astoken ring, FDDI, and ARCNET[1]. Ethernet hasbeen a relatively inexpensive, reasonably fast, andvery popular LAN technology for several decades.Ethernet uses the CSMA/CD access method to handlesimultaneous demands. The most commonly installedEthernet systems are called 10BASE-T and providetransmission speeds up to 10 Mbps. Devices areconnected to the cable and compete for access using aCarrier Sense Multiple Access with CollisionDetection (CSMA/CD) protocol. Gigabit Ethernetprovides an even higher level of backbone support at1000 megabits per second (1 gigabit or 1 billion bitsper second). 10-Gigabit Ethernet provides up to 10billion bits per second. The main aim of the paper isto study the process of developing verilog code forEthernet IP core. This IP core is prototyped usingXilinx Virtex5FX70T FPGA. The prototyping isdone by using the Xilinx tool called embeddeddevelopment kit (Xilinx EDK).It is a suite of toolsthat enables us to design a complete embeddedprocessor system for implementation in a XilinxField Programmable Gate Array (FPGA) device. Thepacket is captured using a network packet analyzercalled Wireshark.II.BACKGROUND2.1.INTRODUCTION TO NETWORKINTERFACE MODELS AND ETHERNET FRAMEFORMATInterconnection of two or more networks forms aninternetwork. The communication between devicespresent in an internetwork presents certain
  2. 2. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731369 | P a g echallenges. For example, devices manufactured bydifferent manufactures need to follow certainconsistent standards to be able to communicateproperly. This led to the development of certainreference models. The network models set a standardas to how information is to be sent over a network.The reference models divide the functions of anetwork into layers. Layers are arranged to be asindependent as possible, with a minimum set ofinformation passing between layers. Each layer (n-1)provides a certain set of services to the layer above it(n), shielding the actual implementation details fromthe above layers. The two most popular referencemodels are OSI reference model and TCP/IPreference model. The OSI reference model providesstandardization for the protocols to be used indifferent layers. OSI (Open Systems Interconnection)model is called so because it is concerned with theinterconnection of systems which are open forcommunication with other systems. The OSIreference model has seven layers.Ethernet is concerned with physical and data linklayers of OSI model. The physical layer isresponsible for converting the data from the form inwhich it is represented in the data link layer (frame)to the form in which it is transmitted over thephysical medium (raw bits)[5]. It provides thehardware required to send and receive data over thephysical medium. This hardware includes signalencoders, line drivers, clock synchronizers, etc.,.Thislayer also defines the electrical, mechanical andtiming specifications for these devices that enabletransfer of data over the communication channel.These include line impedances, pin voltages, cablingspecifications like cabling type, cabling distance, etc.The data link layer is responsible for transfer of databetween stations within a network. The main task ofthe data link layer is to convert the incoming datainto frames. The other functions include error control,addressing, control of access to the shared mediumand flow control. Each frame contains destinationand source addresses which allow identification ofthe sending and the receiving stations on thenetwork[7].The data link layer is divided into two sub-layersnamely the Media Access Control sub-layer and theLogical Link Control layer. The Logical Link Controlsub-layer acts as interface between physical layer andthe higher layer protocols. The data link layer isdivided into media access control (MAC), logicallink control (LLC) and the optionalMAC control sub layer, as shown in Figure 1(a). Theoptional MAC control sub layer provided a structurewith full-duplex flow control[8]. The MAC sub layeradapts LLC sub layer to different media accesstechnologies and physical media. And its mainfunctions are assembling or disassembling data andthe managing of media attaching. The formerincludes the combining of the frame before sendingand the error detection during receiving or afterhaving received. The latter includes the mediadistribution (i.e. collision avoidance) and competitionprocessing (i.e. conflict processing)[3].Figure1: OSI reference model and ethernet frameformat.The Ethernet data frame format is shown in Figure1(b).The preamble is used for synchronization whilesending and receiving data, which includes sevenbytes of 10101010.The start frame delimiter (SFD,10101011) indicates the beginning of a frame. Theleast significant bit (LSB) of the destination addressin destination/source address is used to determineunicast (‘0’) or multicast (‘1’). The length/typespecifies the length or transmission type of data to betransmitted and received. These data is provided bythe upper layer protocol. The PAD is used to ensurethat the length of frame is at least 64 bytes. Bycalculating the CRC [4] of destination/sourceaddress, length/type, the data to be transmitted andreceived and the filling bits, we can get the value ofthe frame check sequence (FCS)[2].2.2ETHERNETMEDIA ACCESS CONTROLLEREthernet protocol is concerned with bottomtwo layers of the OSI reference model. They are theData link layer and the physical layer. The Data LinkLayer is divided into two sub-layers. They are:1. Logical Link Control layer and2. Media Access Control sub-layer.The main functions of the logical link control layerare flow control and multiplexing the protocolstransmitted over the Media access control sub-layerwhile transmitting and decoding them whilereceiving[3]. Ethernet Media access controllerimplements the functions of the Media access controlsub layer. The functions of the physical and data linklayers have been illustrated in Figure2.The functions of an Ethernet MAC (Media accesscontrol) can be summarised as follows:a) Channel access controlb) Framingc) Error detectiond) Addressing
  3. 3. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731370 | P a g ee) IFG implementationFigure 2: Functions of data link layer2.3 CARRIER SENSE MULTIPLEACCESS/COLLISION DETECTION PROTOCOLCSMA/CD (Carrier Sense Multiple Access withCollision Detection) protocol. In this paper,CSMA/CD protocol has been used to implementHalf-Duplex transmission. This protocol provides aneffective way for multiple nodes to access a sharedmedium. According to this protocol, every node onthe network has equal access to the channel[5]. Anode (station) which wants to transmit a frame has tofirst sense the channel to check if another node istransmitting (carrier sense). If the channel is idle,then the node will broadcast after waiting for aninterframe gap of 96 bit times. A collision may stilloccur due to the channel propagation delay (i.e., twonodes may not hear each other’s transmission). In thiscase, the node has to detect if is message wasdestroyed (collision detection). The node thensends a jam signal for 512 bit times to intimate to thestations on the network that a collision has occurred.The station then waits for a random amount of timecalled the back off period before attempting totransmit again. The CSMA/CD protocol follows abinary exponential back off strategy. This means thatif a collision has occurred n times, (i.e., if n attemptshave been made by a node to transmit) then, the nodechooses a random number k from the set {0, 1, 2…(2n-1)}. The node waits for a time equal to theproduct k*512 bit times before it attempts to transmitagain. The bit time is 0.1 µsec for 10Mbps Ethernetand 0.01 µsec for 100Mbps Ethernet. The maximumvalue of k is 1024. If the node does not sense anycollision throughout the duration of its framepropagation, then the node is done with its frametransmission[6].2.4 MEDIA INDEPENDENT INTERFACE (MII)Media Independent Interface (MII) is astandard interface used to connect aEthernet(10/100Mb/s) MAC to a PHY chip. Mediaindependent means that different types of PHYdevices can be connected to different media (i.e.twisted pair, copper, fiber optic.) without replacing orredesigning the MAC hardware. Any MAC may beused with any PHY, independent of the transmissionmedia since the MII bus which is standardized asIEEE 802.3u connects different types of PHYs toMedia Access Controllers.MII bus transfers datausing 4-bit words(i.e..nibble (i.e. 4 transmit data bits,4 receive data bits) in each direction[9].2.5 ETHERNET PHYPHY is the physical interface transceiverwhich is often called as Phyceiver operates atphysical layer of the OSI network model. The IEEE802.3 standard defines the Ethernet PHY. It complieswith IEEE 802.3 specifications for both 10BaseT and100BaseTX. PHY connects a link layer device whichis often called as a Media Access Control or MACaddress to the physical medium. PHY chip providesphysical and analog signal access to the link, which iscommonly found on Ethernet devices[10]. A PHYdevice includes Physical Coding Sub layer (PCS),Physical Medium Attachment (PMA) and PhysicalMedium Dependent (PMD) layer. The data that isbeing transmitted and received is encoded anddecoded by Physical Coding Sub layer. The mainfunctionality of PHY is to handle how the data isactually moved to/from the wire. The PHY provideseither 10 or 100-Mbps operation and can be a set ofintegrated circuits (or a daughter board) on anEthernet port, or an external device supplied with aMedium Independent Interface (MII) cable that plugsinto an MII port on a100BaseT device (similar to a10-Mbps Ethernet transceiver). It contains all theactive circuitry required to implement the physicallayer functions to transmit and receive data onstandard CAT 3 and 5 unshielded twisted pair.III.ARCHITECTURE OF 10/100EMBEDDEDETHERNET CONTROLLERThe controller is mainly composed oftransmit module, receive module, dual portRAM,CRC generator and checker module, fifo,transmit and receive control logic.
  4. 4. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731371 | P a g eFigure3:Architecture of Ethernet controller(Solid line: Architecture of full duplex ethernetcontroller Solid+dotted line: Architecture of halfduplex ethernet controller)1.TRANSMITThe Ethernet transmitter receives a 32-bitinput data from the processor through PLB interface.This 32-bit data is given as input to dual port RAMwhich is asynchronous since the write and readoperations are controlled by different clocks. Fastethernet supports nibble wise transmission. The 4-bitoutput is given to crc generator module whichperforms crc computation using 32-bit crcpolynomial. Then crc output, 4-bit output from dpram, prm and sfd all are routed to mux. The multiplexerroutes the incoming data to the output of the Ethernettransmitter based on the select input received fromthe Transmit control state machine.2.RECEIVEAs long as the Phy_dv is high ,the data isreceived and crc is computed. If the checksum valueof both matches, then the packet passes else thepacket gets discarded.(a) (b)Figure4:(a)Full duplex transmit flow(b)full duplexreceiving flowFigure 5: half duplex transmit flowIV. SIMULATION RESULTS
  5. 5. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731372 | P a g eFigure 6:full duplex waveformFigure 7:Transmitted packet captured in wiresharkFigure8:Received packet captured in WiresharkFigure 9:half duplex waveformV. CONCLUSIONThis paper simply focuses on the applicationor simulation of Ethernet MAC IP (IntelligenceProperty) and it provides a design method of 10/100Mbps Ethernet controller based on embedded.Through software simulation and hardwareverification, the design of the Ethernet controller iseffective and it can be applied in the embeddednetwork systems. Since the embedded GigabitsEthernet has been not widely applied at present,studying the Gigabits Ethernet controller should bethe next step.VI. FUTURE WORKTraditionally TCP/IP is implemented insoftware and executed on a processor. With theadvent of higher bandwidth networks this has becomea major bottleneck in data transfer as the processormust spend more of its time handling incomingframes rather than running user algorithms. This
  6. 6. N.Prathima, K.HariKishore, Dr.Fazal Noorbasha / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp. 1368-13731373 | P a g eperformance degradation negatively impacts networkefficiency and is inconsistent with real timeapplications. To solve this more functions are nowbeing offloaded in to dedicated networks. So we canoffload checksum calculation to hardware so as todecrease the processor clock cycles and increase theperformance. Also, 1Gbps and 10Gbps EthernetMedia Access Controller can be implemented.REFERENCES[1]. Jos C Antonio Moreno Zamora, Pedro JoseRodriguez Corrales and Juan Manuel SanchezPCrez et al. ‘Design of a parametrizable lowcost Ethernet MAC core for Soc Solutions’,IEEE publication, 2003.[2]. Ilija Hadzic, ‘Hierarchical MAC Address Spacein Public Ethernet Networks’, Bell Labs, LucentTechnologies, IEEE publication 2001.[3]. Louis Litwin, ‘Resolving multi-access channelcontention in a broadcast Network, IEEEpublication, 2001.[4]. Richard F. Hobson, Keith L. Cheung, “A High-performance CMOS 32-Bit Parallel CRCEngine,” Solid-State Circuits, IEEE, 1999.[5]. Jose Antonio Moreno Zamora, etc, “Design of aparametrizable low cost Ethernet MAC core forSoc solutions,” System-on-Chip, 2003.[6]. Bin Lin and Elvino S. Sousa, ‘A MODIFIEDCSMA-CD PROTOWL FOR HIGH SPEEDCHANNELS’, IEEE publication, 1990.[7]. Rich Seifert, Jim Edwards, ‘The All NewSwitch Book’, Wiley publishing, Inc.[8]. E. ARTHURS AND B. W. STUCK, ‘AModified Access Policy for ETHERNET”Version 1.0 Data Link Layer’, IEEEpublication, 1984.[9]. Howard M. Frazier, Jr. Sun MicrosystemsComputer Company 2550 Garcia Ave.Mountain View, CA 94043 Media Independentinterface, Concepts and Guidelines, IEEEpublication.10]. Andrew S. Tanenbaum, Computer Networks,Fourth Edition,PearsonEducation,Inc.

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