H33038041

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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

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H33038041

  1. 1. K.Umadevi, P.Vishnu, B.Kailasam / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.038-04138 | P a g eEfficient Clocking System Using Sequential Elements With LowPower ConsumptionK.Umadevi P.Vishnu B.KailasamM.TECH (ES) Assistant Professor ,SCET Assistant Professor,VITS(N6)ABSTRACTLow power flip-flops which plays a vitalrole for the design of low-power digital systems.Flip flops and latches consume a large amount ofpower due to redundant transitions and clockingsystem. In addition, the energy consumed by lowskew clock distribution network is steadilyincreasing and becoming a larger fraction of thechip power. Almost, 30% - 60% of total powerdissipation in a system is due to flip flops andclock distribution network. In order to achieve adesign that is both high performances while alsobeing power efficient, careful attention must bepaid to the design of flip flops and latches. Wesurvey a set of flip flops designed for low powerand High performance.Keywords: Flip-flop, Low Power, Clocking system.I. INTRODUCTIONIn the past, the major concerns of the VLSIdesigner were area, performance, cost andreliability. Power consideration was mostly of onlysecondary importance. In recent years, however, thishas begun to change and, increasingly, power isbeing given comparable weight to area and speedconsiderations. One of the important factors is thatexcessive power consumption is becoming thelimiting factor in integrating more transistors on asingle chip or on a multiple-chip module. Unlesspower consumption is dramatically reduced, theresulting heat will limit the feasible packing andperformance of VLSI circuits [1], [2] and systems.Most of the current designs are synchronous whichimplies that flip-flops and latches are involved inone way or another in the data and control paths.One of the challenges of low power methodologiesfor synchronous systems is the power consumptionof the flip-flops and latches. It is important to savepower in these flip-flops and latches withoutcompromising state integrity or performance.Power Consumption is determined by severalfactors including frequency f, supply voltage, dataactivity, capacitance, leakage and short circuitcurrent.P= Pdynamic + Pshort circuit + PleakageIn the above equation, Pdynamic is called theswitching power p= αCv2f. Pshortcircuit is the shortcircuit power which is caused by the finite rise andfall time of input signals, resulting in both the pullup network and pull down network to be ON for ashort period Pshort circuit = Ishort circuit * Vdd. Pleakage isthe leakage power. With supply voltage scalingdown, the threshold voltage also decreases tomaintain performance. However, this leads to theexponential growth of the subthreshold leakagecurrent.Pleakage current = Ileakage current * Vdd.Based on the above factors, there arevarious techniques for lowering the powerconsumption shown as follows: In Double EdgeTriggering, Using half frequency on the clockdistribution network will save approximately half ofthe power consumption on the clock distributionnetwork. However the flip-flop must be able to bedouble clock edge triggered. Double clock edgetriggering method reduces the power by decreasingfrequency. Using a low swing voltage on the clockdistribution network can reduce the clocking powerconsumption since power is a quadratic function ofvoltage. To use low swing clockDistribution, the flip-flop should be a low swingflip- flop. The low swing method reduces the powerconsumption by decreasing voltage.There are two ways to reduce the switchingactivity: conditional operation (eliminate redundantdata switching: conditional capture flip-flop(CCFF)) or clock gating, conditional discharge flip-flop (CDFF). In Conditional Operation, there areredundant switching activities in the internal node.When input stays at logic one, the internal node iskept charging and discharging without performingany useful computation. The conditional operationtechnique is needed to avoid the redundantswitching. In Clock Gating, when a certain block isidle, we can disable the clock signal to that block tosave power. Both conditional operation and clockgating methods reduce power by decreasingswitching activity.In Reducing Short Current Power, splitpath can reduce the short current power, since p-MOS and n-MOS are driven by separate signals. InReducing Capacity of Clock Load, 80% of nonclocked nodes have switching activity less than 0.1.
  2. 2. K.Umadevi, P.Vishnu, B.Kailasam / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.038-04139 | P a g eThis means reducing power of clocked nodes isimportant since clocked node has 100% activity.One effective way of low power design for clockingsystem is to reduce clock capacity load byminimizing number of clocked transistor. Any localclock load reduction will also decrease the globalpower consumption. This method reduces power bydecreasing clock capacity.II. SURVEYED TECHNIQUE FORREDUCING CLOCK CAPACITYMost of the flip-flops presented here aredynamic in nature, and some internal nodes areprecharged and evaluated in each cycle withoutproducing any useful activity at the output when theinput is stable. Reducing this redundant switchingactivity has a profound effect in reducing the powerdissipation, and in the literature many techniqueswere presented for this purpose . A brief survey ofsuch techniques is conducted in this work, and themain techniques were classified as follows:2.1 Conditional Capture Flip FlopConditional Capture technique is proposedfor disabling redundant internal transitions. Thistechnique achieves significant power reduction atlittle or no delay penalties. Motivation behindConditional Capture technique[3] is the observationthat considerable portion of power is consumed fordriving internal nodes even when the value of theoutput is not changed (corresponding to low inputactivities). It is possible to disable internaltransitions when it is detected that they will have noeffect on output. But the drawback is increased set-up time for sampling zero (low level) and alsoheavier load is presented to the Q output of the flipflop.2.2 Conditional Precharge Flip FlopFor overcoming the disadvantage inConditional Capture Flip Flop[3], Conditional pre-charge flip flop is proposed One of the mostimportant contributions of this work is related topreventing unconditional pre-charge operation of theinternal node, tightly connected to excessive powerdissipation of the circuit. This is accomplished bycontrolling the return of internal node to inactive(high) state, allowing the internal node to stay at lowlevel until input condition is changed. This approachefficiently eliminates the unnecessary transitions ofthe internal node as well as race condition at theoutput. There are two main disadvantages: One isintroducing another critical path for low input levelcapture. Another drawback is increasing the outputload due to the feedback, which although minimalsize transistor can be used, being out of the criticalpath, can affect total propagation delay.2.3 Conditional Discharge Flip FlopConditional Discharge Flip-flop (CDFF)[4]not only reduces the internal switching activities,but also generates less glitches at the output, whilemaintaining the negative setup time and small Q-to-output delay characteristics. With a data-switchingactivity of 37.5%, this flip-flop can save up to 39%of the energy with the same speed. In this Flip-flop,the extra switching activity is eliminated bycontrolling the discharge path when the input isstable HIGH. In this scheme, an n-MOS Transistoris inserted in the discharge path with the high-switching activity. When the input undergoes aLOW-to-HIGH transition, the output changes fromHIGH to LOW. This transition at the outputswitches off the discharge path of the first stage toprevent it from discharging or doing evaluation insucceeding cycles as long as the input is stable. Butthe disadvantage is it used 15 clocked transistors.2.4 Conditional Data Mapping Flip FlopConditional Data Mapping Flip flop usedonly seven clocked transistors, resulting in about50% reduction in the number of clockedtransistors,hence CDMFF[5] used less power thanCCFF and CDFF as shown in fig 2.1.Note thatCDFF used double edge clocking. For simplicitypurposes, we did not include the power savings bydouble edge triggering on the clock distributionnetwork. This shows the effectiveness of reducingclocked transistor numbers to achieve low power,Since CDMFF outperforms CCFF and CDFF. But itmakes very difficult to apply the Double edgetriggering and also it cannot be used in a low swingenvironment. Moreover it reduces the number ofclocked transistors but it has redundant clocking aswell as floating node. So we can move into theclocked pair shared flip-flop.FIGURE 2.1:CDMFF.
  3. 3. K.Umadevi, P.Vishnu, B.Kailasam / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.038-04140 | P a g e2.5 CLOCKED PAIR SHARED FLIP FLOP(CPSFF)Clocked Pair Shared flip-flop (CPSFF)[6]to use less clocked transistor than CDMFF and toovercome the floating problem in CDMFF as shownin fig 2.2. In the clocked-pair-shared flip-flop,clocked pair is shared by first and second stage. Analways on p-MOS, P1, is used to charge the internalnode rather than using the two clocked pre chargingtransistors (P1,P2) in CDMFF. Comparing withCDMFF, a total of three clocked transistors arereduced, such that the clock load seen by the clockdriver is decreased, resulting in an efficient design.CPSFF uses four clocked transistors rather thanseven clocked transistors in CDMFF, resulting inapproximately 40% reduction in number of clockedtransistors.Figure 2.2: Clocked Pair Shared Flip FlopIII. Proposed Low Power Clocked PassTransistor Flip-Flop DesignBy using the Pass Transistor Logic familyidea we are designing this circuit as well as by usingthe pass transistor logic we are using only oneclocking transistor so it will be Consuming only lesspower in the clock network of the Flip flop whencompared to all other circuits.As well as we are having only 6 Transistorsexcluding the not gates also. So we will be havingmuch reduced power and area when compared to theother two designs. At the same time due to thereduced no of transistor count we can reduce thedelay oriented things also. Thus we are reducing theoverall switching delay and power, areaconsumption. So this circuit will be acting as goodsequential elements when compared to other flip-flop design.The graph represents the input & outputcharacteristics of our proposed system from that wecan clearly understand how it works as negativeedge triggered flip-flop. There is some nano secondsdelay is there even though it’s a negligible amountonly. Those delays can be further reduced byreducing the sizes of the transistor we are using inthis circuit. Or by reducing the nano metertechnology also we can reduce the constraints. TheLayout design of the proposed new flip-flop isshown in the figure 3.2 the area of that is mentionedat the downside of the layout.Figure 3.1: Proposed Low Power Clocked PassTransistor flip-floPFigure 3.2: Layout of theLCPTFF Proposed DesignThus the Our Proposed Low PowerClocked Pass Transistor flip-flop (LCPTFF Fig.3.1)design shows much less power & Area constraintsthan the Existing two Flip-Flop designs. As well asthe Proposed design will be having very less clockdelay when compared to all other circuits. So it canbe used in all the future sequential elements for highspeed low SOC’c manufacturing.
  4. 4. K.Umadevi, P.Vishnu, B.Kailasam / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.038-04141 | P a g eIII. TabulationPower & Area Comparison Table usingCMOS012 umFLIPFLOPNo. ofTransistorPowerConsumptionAreaConsumptionWidthCDMFF7 11.380µW 278.1µm2 31.3µmCPSFF 4 6.184µW 207.8µm2 22.2µmLCPTFF4 4.663 µW 138.1µm2 16.4µmThus the Our Proposed Low PowerClocked Pass Transistor flip-flopdesign shows muchless power & Area constraints than the Existing twoFlip-Flop designs. As well as the Proposed designwill be having very less clock delay when comparedto all other circuits. So it can be used in all thefuture sequential elements for high speed lowSOC’c manufacturing.IV. CONCLUSIONIn this paper, a variety of design techniquesfor low power clocking system are reviewed. Oneeffective method, reducing capacity of the clockload by minimizing number of clocked transistor, iselaborated. Following the approach, one novelCPSFF is proposed, which reduces local clocktransistor number by about 40%. In view of powerconsumption of clock driver, the new CPSFFoutperforms prior arts in flip-flop design by about24%. Furthermore, several low power techniques,including low swing and double edge clocking, canbe explored to incorporate into the new flip-flop tobuild clocking systems.REFERENCES[1] C. L. Kim and S. Kang, “A low-swingclock double edge-triggered flip-flop,”IEEE J. Solid-State Circuits, vol. 37, no. 5,pp. 648–652, May 2002.[2] J. Rabaey, A. Chandrakasan, and B.Nikolic, Digital Integrated Circuits.Englewood Cliffs, NJ: Prentice-Hall, 2003.[3] B. Kong, S. Kim, and Y. Jun, “Conditionalcapture flip-flop for statistical powerreduction,” IEEE J. Solid-State Circuits,vol. 36, no. 8, pp.1263–1271, Aug. 2001.[4] P. Zhao, T. Darwish, and M. Bayoumi,“High-performance and lowpowerconditional discharge flip-flop,” IEEETrans. Very Large Scale Integr. (VLSI)Syst., vol. 12, no. 5, pp. 477–484, May2004.[5] C. K. Teh, M. Hamada, T. Fujita, H. Hara,N. Ikumi, and Y. Oowaki, “Conditionaldata mapping flip-flops for low-power andhigh-performance systems,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst.,vol.14, no. 12, pp. 1379–1383, Dec. 2006.[6] Peiyi Zhao, Jason McNeely,WeidongKuang, Nan Wang, and“Design ofSequential Elements for LowPowerClocking System” IEEE TransactionMay 2011

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