Published on

  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide


  1. 1. Deepthi.P, Vinay.P / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 5, September- October 2012, pp.1107-1110 Pseudo Exhustive Test Patterns For Online And Offline Bist On Fpga Deepthi.P, Vinay.P Department Of Ece, Jntuh, HyderabadAbstract In this paper we discuss the built-in self- Circuit-Under-Test (CUT). This is crucial to thetest (BIST) or built-in test (BIT) techniques quality component of testing. BIST can overcomeforreconfigurable FPGAs.The FPGA is pin limitations due to packaging, make efficientconfigured with the BIST logic during offline use of available extra chip area, and provide moretesting. Once the test is completed the BIST detailed information about the faults present. Aconfiguration is erased and the PGA is generic approach to BIST is shown in Fig 1. On areconfigured to the original operation. In offline very basic level, BIST needs a stimulus (thethe BIST logic for the programmable logic blocks Test Pattern Generator - TPG), a circuit to beand interconnections are mentioned. tested (CUT) and a way to analyze the results In online, the original operation of (ORA). Additionally, there may be compressionFPGA can be configured as a processor ALU schemes for the TPG and the ORA [2-3].with built-in-self test (BIST) feature. Key features of the design includingFPGA array structure, it’s configuration forBIST, ALU, application of design with RISCarchitecture, data path, and simulation resultsare presented. The design is implemented usingVHDL and verified on Xilinx ISE simulatorKeywords-RISC, BIST, VHDL, FPGA programmable logic blocks, interconnects and I/O blocks used to implement bothI.INTRODUCTION combinational and sequential logic by programming Field ProgrammableGate Arrays (FPGAs) these circuit elements. There are several differentfeature their ability to be configured in the field FPGA testing strategies. The main test techniqueto implement an arbitrary desired function that we are going to address is built in self testaccording to the real-time demands. This ability (BIST) method Reduced Instruction Set Computerof FPGAs can help people to achieve a faster (RISC) focuses on reducing the number anddesign cycle, lower development costs and a complexity of instructions in the machine. Anreduced time-to market .Therefore, are widely used arithmetic logic unit is a digital circuit that performsin many applications such as networking, arithmetic and logical operations .The ALU is astorage systems, communication, and adaptive fundamental building block of the central processingcomputing. unit of a computer. An ALU loads data from Field programmable Gate Arrays (FPGA) input registers, an external control unit then tells theare devices consisting of an array of proposed in [5]. ALU what operation to perform on that data, andThese methods are applicable only to reconfigurable then the ALU stores it result into an output register.FPGAs.In today’s Integrated Circuits (ICs), Built-In- Self Test (BIST) is becoming increasingly The organization of the paper is as follows:important as designs become more and more In Section 2, we present the FPGA arraycomplicated. Keeping the structural fault structure, BIST for CLB and interconnections. Incoverage high along with maintaining an section 3, we represent BIST feature ALU, RISCacceptable design overhead is critical. It is processor architecture, and data path of theimportant to achieve a high proposed design. Simulation results are alsolevel of reliability with minimum cost and time. It is provided in this section. The paper concludes inwith this goal in mind that BIST has become a section 4.major design consideration in Design-For-Testability (DFT) methods. BIST is beneficial in II.BUILT IN SELF TEST (BIST)many ways: First, it can reduce dependency on The Xilinx FPGA uses symmetricalexternal Automatic Test Equipment (ATE). In array structure and the logic blocks are calledaddition, BIST can provide at speed, in system Configurable Logic blocks (CLB). Figure 2 showstesting of the the basic array structure of a Xilinx FPGA [1]. 1107 | P a g e
  2. 2. Deepthi.P, Vinay.P / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 5, September- October 2012, pp.1107-1110 reconfigures the FPGA with the BIST logic and 2) initiates the test. 3) The BIST logic generates test patterns within the FPGA and 4) analyzes responses and generates the pass/fail output. 5) The test controller reads the test results. In steps 1, 2, 5 the test controller interacts with the FPGA through the I/O pins and steps 3, 4 are internal to the FPGA.Fig.2.FPGA ARRAY STRUCTUREA.TESTING THE CLB The CLB consists of 1) Multiplexers and 2) Fig.3.FPGA configuration for BISTLUT which together form the combinational partand 3) Flip flops which form the sequential For conducting the self test in steps 3 and 4module. some of the CLBs in the FPGA are configured as test pattern generators (TPGs) and output response The reprogrammable nature of FPGAs can analyzers (ORAs). The remaining CLBs arebe used to an advantage for BIST. The FPGA tested with pseudo exhaustive test patterns asis configured with the BIST logic during offline described in [5]. These CLBs are referred to astesting. Once the test is completed the BIST the blocks under test (BUTs). As every BUT inconfiguration is erased and the FPGA is an FPGA is identical, the ORA has to compare thereconfigured to the original operation. This implies outputs of any two BUTs. Only if the two BUTs failthat there is no overhead attached to the BIST in in an identical manner will the fault escapeterms of additional circuitry or space. The BIST detection which is highly unlikely. Another caseis applicable at all levels (wafer, package, board, when the tests would be incomplete is when the twosystem) and is performed at normal operating BUTs are fed by the same faulty TPG. Thisfrequency [4]. problem is solved by careful configuration which ensures that an ORA compares BUTs tested A test controller is used to configure by different TPGs and that all the TPGs arethe FPGA with the BIST logic, start the testing and synchronized. Figure 3 shows the configurationread the test results. Additional memory is required for testing [6].to store the BIST configuration as well as the The BUTs are completely tested for alloriginal FPGA configuration that is restored after modes of operation in one test session. After thethe FPGA has been tested. This is the main cost BUTs are tested the roles of the CLBs are reversedof the BIST;but memory is available in the test and the BUTs become TPGs and ORAs and vicemachine and hence no additional resources are versa and the test session is repeated. At least 2required of the device under test. Also as the testing test sessions are required to test the CLBs. In oneis at-speed, the testing time is low and so the cost of test session as all the BUTs are tested in parallel thetesting is low. The BIST time required for the BIST does not depend onconfiguration is independent of the function the size of the FPGA.implemented in the FPGA, and is dependent only During most of the test configurations theon the FPGA architecture so all the FPGAs of TPGs behave as m-bit binary counters to supplythe same type can be tested by the same BIST exhaustive test patterns to the m-input BUTs. As theconfiguration. This reduces cost of testing because numbers of inputs are more than number ofof reusability of the test. outputs many CLBs are required to generate the m-bit counter. As different TPGs are required for The main steps of carrying out BIST on a BUTs compared by the same ORA the number ofFPGA are: 1) The test controller machine TPGs required is equal to the number of BUT 1108 | P a g e
  3. 3. Deepthi.P, Vinay.P / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 5, September- October 2012, pp.1107-1110outputs that can be compared by one ORA. An does the actual operation of the ALU, and theORA is built from an LUT for comparing inputs Testing Architecture, which comes into play onlyand a flip-flop that provides feedback to the LUT during testing. The Operation Architecturesas shown in figure 3. The flip-flop records the first consists of five units, 4-bit Carry Lookerror detected and also disables further Ahead adder (CLA), and a 4-bit AND, OR,XORcomparisons by the LUT. All the inputs of the and INVERTER gates. There is a PreCLA toLUT except one for the feedback are connected prepare the inputs based on the arithmeticto the BUT outputs and the LUT compares the operation to be done. There is a MUX which usesvalues and if there is a mismatch it records it the select pins to select one of the results from theon the flip-flop. above five units. The Testing Architecture has a ROM which has the discovered test patterns stored The Xilinx XC4000 series has two 4- input in. There is an address decoder to select whichLUTs in a CLB and two flip-flops. So three of the test patterns will be applied. There is acomparisons (number of inputs/LUT - 1) per LUT TestMUX, which depending on the value on thecan be done and hence the number of TPGs TestMode pin will present the test pattern or therequired is three. The number of inputs and outputs actual inputs to be operated upon, toper CLB are 12 and 5 respectively. To generate a the Operation Architecture.12-bit counter 12 flip-flops i.e. 6 CLBs are requiredfor a TPG. All the three parts viz. LUTs, flip flopsand multiplexers of the FPGA are tested and thefault coverage is 100%.B.BIST for interconnect In [7], the BIST method is extended fortesting the interconnect faults in both local(multiplexer PS) and global (switch matrix) routing.The fault model used covers all stuckoff (stuck-on), stuck-open (stuck-short), stuck-at 0/1 in boththe wire segments and the PSs. A group of kwires and PSs are combined to form the wiresunder test (WUT), and exhaustive testing is doneby applying all 2k patterns to every group. Such a Fig .4. ALUtest that applies 0 and 1 values at one end of thewire and expects the same value at the other end can V.APPLICATIONdetect any stuck-open fault on a wire with a closed The RISC processor presented in this paperPS, and also any stuck- at faults. To test the stuck- consists of three components. Those are, the ALUon fault of a PS, opposite values should be applied with BIST feature, the Data Path, and the both the wire segments associated with that The Central Processing Unit (CPU) has 33PS. Multiplexer-based PSs can be tested using instructions.functional tests as before, by select all possibledata-inputs and with each data being tested for both0 and 1 values. The BIST configuration is similar tothe one used for testing CLBs described in aboveinvolving TPGs and ORAs. Test patterns generatedby a TPG are applied to two WUTs and theoutputs are compared by ORA. The path fromthe TPG to the ORA consists of the WUTs andintermediate PLBs that are configured to passdata from inputs to outputs. This achieves bothlocal and global interconnect test coverage. Thenumber of configuration phases required is reducedas multiple WUTs are tested in parallel. Thismethod has the same shortcomings as the BISTfor CLBs, i.e. identical faults appearingon WUTs compared by the same ORA will escape Fig.5.RISC processor architecturedetection.IV .BIST feature ALU The architecture of the ALU consists oftwo parts, the Operation Architecture, which 1109 | P a g e
  4. 4. Deepthi.P, Vinay.P / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 5, September- October 2012, pp.1107-1110 and operation and testing ALU has been designed. Every instruction is executed in two clock cycles and corresponding result is verified with test vectors in ROM. The design is verified through exhaustive simulations. REFERENCES [1] Stephen Brown and Jonathan Rose, Architecture of FPGAs and CPLDs: A Tutorial, University of Toronto. [2]. R. N. Noyce and M. E. Hoff, “A History of Microprocessor Development at Intel,” IEEE Micro, vol. 1, no. 1, 1981, pp. 8-21. [3]. J.L. Hennessy, "VLSI Processor Architecture," IEEE Trans.Computers, vol. Fig.6. Data path for RISC Processor C-33, no. 12, Dec. 1984, pp. 1221-1246. [4] C. Stroud, S. Konala, P. Chen, M. The data to the processor is obtained from Abramovici, Built-In Self-Test of Logicthe external world. The data is processed by the Blocks in FPGAs (Finally, a Free Lunch:processor by apply control signals. The control BIST Without Overhead!), Proc. 14thsignal is designed in architecture of processor. After VLSI Test Symposium, pp. 387-392, 1996.processing the data its again sent along the data [5] E. McCluskey, Verification Testing - Apath of processor to external world. Pseudoexhaustive Test Technique, IEEE Transactions on Computers, Vol. C-33, No.V.SIMULATION RESULTS OF RISC 6, pp.541-546, June 1984. The design is implemented using VHDL [6] R.Sharama,v.k.sehgal,nitin.pranavand verified on Xilinx ISE simulator. bhasker,ishita verma- Design and Implementation of a 64-bit RISC Processor using VHDL, UKSim 2009: 11th International Conference on Computer Modelling and Simulation. [7] C. Stroud, S. Wijesuriya, C. Hamilton, M. Abramovici,Built-in Self Test of FPGA Interconnect,Proc. IEEE International Test Conference., pp.404-411, 1998. Fig.7. simulation resultsIV. CONCLUSION The most important requirement of a goodFPGA test is that it should be independent of theend-application and the array size. BIST usespseudo exhaustive test pattern that providesmaximum fault coverage without assuming afault model. Two test configurations arerequired for complete testing and testing isconducted at-speed. Other advantages that BISToffers is that it does not require additional storagespace for the test vectors, since the CLBs areconfigured as TPGs to generate the test vectors.The BIST approach generates the test vectorsinternally. The comparator based BIST providescomplete test coverage for global and localrouting but fails to detect identical faultsoccurring in two WUTs compared by the sameORA. RISC processor with 33 instruction set 1110 | P a g e