Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752746 | P a g eComparative Approach to Conventional and Fast Locking DigitalPhase Locked Loops*Raman Bondare, **Rajesh Langote*Shri Ramdeobaba College of Engineering & Management, India**Priyadarshani College of Engineering, IndiaAbstractA digital phase-locked loop (DPLL) isdesigned using 180 nm CMOS process and a 3.3V power supply. It operates in the frequencyrange 200 MHz–1 GHz. The DPLL operationincludes two stages: (i) a novel coarse-tuningstage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. Theflash portion of the DPLL is made up offrequency comparators, an encoder and adecoder which drives a multiple charge pump(CP)/low pass filter (LPF) combination. Designconsiderations of the flash DPLL circuitcomponents as well as implementation usingTanner design tools are presented. Spectrasimulations were also performed anddemonstrated a significant improvement in thelock time of the flash DPLL as compared to theconventional DPLL.Keywords — PFD, MCP, LPF, VCO, CP, FC.I. INTRODUCTIONPhase-locked loops (PLLs) arecommonplace in applications like wirelesstransceivers, global positioning systems, clockgenerators and so on. A major characteristic of thePLL is the lock time; it is the time the PLL takes toadapt and settle after a sudden change of the inputsignal frequency.Conventional PLLs inherently take longtime to lock since the output frequency undergoesthe entire iterative process before reaching naturalconvergence; this renders these PLLs unfit forcontemporary high-speed, high throughputapplications needed for information technology.Examples of conventional digital phase-locked loops(DPLLs) using 0.18 mm CMOS process are given in[1, 2]. The DPLL in  is a 55 MHz–1.43 GHz onewith a lock time of 840 ns at 1 GHz and 1.22 ms at1.43 GHz. The DPLL in  is a 1 GHz one with alock time of 643 ns at that frequency. These twoexamples represent the state-of-the-art ofconventional DPLLs using 0.18 mm CMOS process.Fast locking is required for fast frequencyhopping among data bursts in high-speed digitalcommunications . PLLs with low-powerconstraints demand that they be turned off duringinactivity, but then require that they lock quicklywhen turned back on. Fast locking is therefore anecessity for spread-spectrum communications,cellular phones, clock/data recovery circuits and soon. In fast- locking DPLLs, phase locking is speededup via a fast-start mechanism that accounts for mostof the frequency change, whereas the outputfrequency undergoes the above- mentioned naturaliterative convergence process, which characterisesconventional DPLLs, over the remaining very smallfrequency range.Although the literature on PLLs containsseveral thousands of designs and research papers,the literature on fast-locking PLLs is very limited(several tens) because of the more recent greatdemand. Research papers include some well-knowntechniques for PLL fast locking, for example (i)using a non-linear phase detector (PD) to obtain fastlocking and good jitter damping thus overcomingthe problem of requiring a high natural frequencyfor fast locking and a low one for good jitterdamping, (ii) a digital hybrid PLL frequencysynthesizer which provides coarse tuning with aloop filter, fine tuning with a D/A converter (DAC)to control the voltage-controlled oscillator (VCO)and a frequency control word applied to aprogrammable counter and look-up table and (iii) adual-slope PFD based on two loops, one for coarsetuning and one for fine tuning.There is also a number of US patents in theliterature such as (i) US patent # 6,380,810containing a speed-up circuit amplifying adifferential voltage coupled to a filter capacitorcreating a coarse-tune VCO voltage via rapidcharging and discharging , (ii) US patent #6,566,966 where the VCO employs a controller anda DAC , (iii) US patent # 6,624,705 whichpresents a PLL with reduced cycle slip duringacquisition; it includes a charge pump (CP) withselectable output current ranges, (iv) US patent #6,624,707 employing gain control via a feedbackcircuit to adjust the loop gain at any specific tuningvoltage and consequently the current gain of thePFD and (v) US Patent # 6,940,356 for a DPLLemploying multiple charge pumps (MCP) .There are a number of industrialcorporations that produce fast-locking PLLs, forexample, Analog Devices Inc. that uses a timer inthe fast-lock mode to determine the time of the widebandwidth, True Circuits Inc. that uses a LockNow! technology and National Semiconductor Inc.that adaptively multiplies the charge-pump current.
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752747 | P a g eThe above literature reveals that fast-lockingDPLLs fall under the following categories: (i)techniques based on a mathematical algorithm toachieve fast convergence, (ii) techniques based onnon-linear characteristics of the CP to change theconvergence rate, (iii) techniques based on afeedback mechanism associated with the PD or theCP and iv) techniques based on using current-modetechniques in lieu of voltage-mode techniques.Section II describes the flash DPLL theoryof operation. This is a novel technique whereby theword ‘flash’ is borrowed from ‘flash A/Dconverters’ to signify very fast achievement of athermometer code that approximates the value of theanalogue input voltage via an array of parallelvoltage comparators; the net result is a very fastADC conversion time of one clock cycle. In theproposed flash DPLL, an analogous array offrequency comparators is used to produce, after avery small delay, a thermometer code thatapproximates the value of applied input frequency.The thermometer code thus continuously detects anypositive or negative hops in the input frequency, andconsequently causes the DPLL to undergo a fast-start mechanism that will ultimately shorten the locktime; a new contribution to the literature on fast-locking DPLLs. It will be useful for applications thatrequire very fast DPLL locking, for example,spread-spectrum communications, cellular phones,clock/data recovery circuits, information technologyand so on.Section III describes the design of the flashDPLL employing both the conventional and fast-locking hardware. Some of the components arestandard circuits, whereas others are only used inthis paper. Section IV describes the implementationand simulation of both the flash DPLL and itsconventional counterpart. Section V providesconclusions of the work.II. BLOCK DIAGRAM OF THE FLASH DPLLThe original block diagram of the novelflash fast-locking DPLL is shown in Fig. 1. Thecircuit quickly and simultaneously compares theinput frequency with many equispaced fixedfrequencies covering the entire anticipated frequencyrange of operation. Now, frequency comparisonresults will be represented by a thermometer code tobe applied to a DAC, the output of which willcontrol the VCO, thus ending the coarse-tuningstage. This stage is followed by a fine-tuning stage,where locking will take place like a conventionalDPLL. It should be noted that during the fine-tuningstage the switch is closed, which may give theimpression that the VCO has two inputs rather thanone. However, the VCO block contains a provisionsuch that when the LPF output is applied to theVCO, the DAC output will be automaticallyswitched out of the VCO, thus there is effectivelyonly one input to the VCO. Since the fine-tuningstage covers a much narrower frequency range,while the fast-locking hardware is disabled, thetransient response of this stage is minimal. Byadding the convergence times of both coarse-tuningand fine-tuning stages, the resulting DPLL lock timewill be much smaller than that had the coarse-tuningstage not existed.This hypothesis fills an important gap in theliterature since it is the counterpart of the conceptgiven in , which achieves fast locking via analgorithm similar to the one used in successive-approximation ADCs. However, the much fasterflash algorithm, as applied to DPLLs, is expected toresult in a significant reduction in lock time at theexpense of additional hardware.Figure 1 Original block diagram of the novel flashDPLLAlthough the concept of this design seemslogical, it was found after building and testing it that,with the switching sequence and circuitry that wereattempted, the CP was not able to react fast enoughto the coarse-tuning stage as expected. It was theneasier to remove the DAC and replace the single CPwith a MCP activated by a decoder which selects theCP suitable for a particular frequency jump (hop) atthe input. The modified block diagram is given inFig. 2, which falls under both categories (i) and (ii)mentioned above in Section I.The flash DPLL operates by monitoringany changes in the input signal frequency (Fin)every, say 20 ns, using an array of, say eight,frequency comparators with reference frequencies(Fref), ranging from 250 MHz to 2 GHz. Once achange in Fin is detected during any 20 ns cycle, anadditional 20 ns cycle is needed to accuratelyestimate the new input frequency, since thefrequency hop takes place at any time during thefirst 20 ns cycle. Thus 40 ns are needed to coarselyestimate the new input frequency. The thermometercode, at the output of the frequency comparatorarray, is applied to a priority encoder which outputsa 3-bit binary code to a decoder, which in turnselects one-out-of-eight charge pumps (CPs)/lowpass filters (LPFs). The LPF output voltage is theninputted into the VCO which produces the closestfrequency to the new input frequency; this marks theend of the coarse-tuning stage. The selected CP/LPFwill stay in use until a new Fin has been detected.
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752748 | P a g eThe remaining time to lock the DPLL is regarded asthe fine-tuning stage, where locking will take placelike a conventional DPLL while the frequencycomparators, encoder and decoder are not affectingcircuit operation. Since coarse tuning sets the VCOfrequency to the closest possible to Fin, the fine-tuning time is thus cut down tremendously, ascompared to the conventional DPLL thus resultingin a much faster lock time.Figure 2 Modified block diagram of the novel flashDPLLIII.DESIGN OF THE FLASH DPLLThe circuit components of the flash DPLL of Fig.2 are given below:A. Phase-frequency detectorThe block diagram of the phase-frequencydetector (PFD) is given in .The outputs UP andDN (Down) depend on the frequency and lead/lagrelationship between the input Fin and Fvco (VCOoutput frequency). When the loop is locked, the UPand DN remain low.B. Voltage-controlled oscillatorA current-starved VCO is built, which isbasically composed of an odd number of inverterstages, as given in . For proper operation, M4(connected to VDD) and M5 (connected to the VCOinput Vcntrl) have to operate in the saturationregion. The VCO oscillation frequency is given by.Where Ctot is the total load capacitance atthe drain of inverters, and t1 and t2 are the chargeand discharge times. A five-stage VCO was usedbecause it requires less input voltage than that of aseven- or nine-stage VCO. Table 1 shows therequired voltages needed to produce a specificfrequency. Two inverters were used at the VCOoutput to give sharp waveform edges.In order to test the VCO, a ramp was usedat the input to allow oscillations to begin. The rampwas set up to 1.36 V. The resulting Fvco was 2 GHzwhich agrees with Table 1.C. MCP and LPFs1) Single CP and LPF: A single CP is shown in Fig.3. A precise current mirror is used to removeinstability and ripple in the control voltage. Theoutput control voltage Vcntrl will increase/decreasedepending on whether the UP/DN pulse occurs. TheCP starting voltage is an important design factorsince it helps in decreasing the lock time of theDPLL. This voltage can be controlled by modifyingthe aspect ratio (W/L) of N1 and P2. The LPF isshown in Fig. 3.TABLE 1VCO FREQUENCY AGAINST VOLTAGE (VCNTRL)Frequency Voltage (Vcntrl)250 MHz 865 mV500 MHz 1.038 V750 MHz 1.14 V1 GHz 1.2 V1.25 GHz 1.25 V1.5 GHz 1.28 V1.75 GHz 1.32 V2 GHz 1.36 VFigure 3 Single CP and LPF2) MCP and LPFs:The MCP design, shown in Fig.4, is madeup of eight individual CPs; each CP has a differentstarting control voltage. The output bits of thedecoder control the MCP. When a single CP isselected, only its pertinent switches close, thusallowing the UP/DN pulses from the PFD to be inputto the CP. Table 2 display the required aspect ratiosto produce the starting voltage levels of the CPs; theoutput of the selected CP (Table 2) has an initialvoltage level which is slightly larger than therequired voltage level for each specific frequency(Table 1). The LPF output voltage Vcntrl is thusinput into the VCO with a slight overshoot to speedup the DPLL. Each CP has its own LPF although allLPFs are identical; this prevents the capacitor from
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752749 | P a g ekeeping the charge of the previously used CP thuseach capacitor starts fresh when a new inputfrequency is detected.D. Frequency comparatorsThe frequency comparator is the mostessential component of the FLASH DPLL. It is whatdetermines which CP to use, thus allowing a fasterlock time. The frequency comparator array is shownin Fig. 5. Depending on the input frequency Fin andthe reference frequencies Fref, the output of eachindividual comparator will be either high ‘1’ or low‘0’. The block diagram of Fig. 7 has one commoninput Fin and seven outputs (A1–A7); it also showsthat each individual frequency comparator has threeinputs (Fin, Fref and Reset). The ‘Reset’ inputreceives a pulse every 20 ns to reset the entire arrayof frequency comparators so that it can begin a newcomparison every 20 ns. The outputs of allcomparators constitute the ‘thermometer code’ to beinputted into the priority encoder.Figure 4 MCP schematicIn this design, a novel frequencycomparator  was attempted; it uses ring countersto determine whether the input signal is slower orfaster than the reference signal. The advantage ofthis type is that it always gives correct comparisonresults regardless of the phase shift between theinput and reference signals. To account for the caseswhen the comparator cannot decide during anarbitrarily allotted time frame (we selected 20 ns),we added a Time-Out flag to the output of thefrequency comparator. The idea is that ‘Time-Out =1’ means that both Fin and Fref are too close to eachother, thus it is a good approximation to assume thatFin >Fref for that particular comparator even if thisis not true and thus the comparator’s decision wouldbe ‘1’; this small error during the coarse-tuning stagewould be accounted for anyhow during the fine-tuning stage of the flash DPLL. The frequencycomparator block of Fig. 7 is made up of seven ofsuch comparator type. Thus, the lowest frequencycomparator (#7) in Fig. 7 compares Fin with Fref7 of500MHz, while the frequency comparator above it(#6) compares Fin with Fref6 of 750MHz and soforth.Figure 5 Block diagram of an array of frequencycomparatorsE. Priority encoderThe purpose of the encoder is to translatethe output signals of the frequency comparator arrayinto a 3-bit binary code that will get inputted into thedecoder. To generate a 3-bit binary code at theoutput, that is, b1–b3 (b1 being the LSB) from aninput array A1–A7 (A1 being the LSB), the designprocedure used is outlined in . The circuit wasimplemented using AND, OR, INVERT logic.TABLE 2STARTING CP VOLTAGE CONTROL OUTPUTPER ASPECT RATIOChargepumpAspect ratio Voltage(Vcntrl),VP2 (W/L) N1(W/L)1 11/0.18 10.5/0.18 1.042 11/0.18 8.5/0.18 1.203 11/0.18 8/0.18 1.264 11/0.18 7.75/0.18 1.295 11/0.18 7.25/0.18 1.356 11/0.18 7/0.18 1.397 11/0.18 6.65/0.18 1.448 11/0.18 6.25/0.18 1.50
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752750 | P a g eIt should be noted that, in our present design usingonly seven frequency comparators, the eight rows ofTable 3 (top to bottom) correspond to the followinginput frequency ranges, respectively: (<500 MHz),(500–750 MHz), (750 MHz–1 GHz), (1–1.25 GHz),(1.25–1.5 GHz), (1.5–1.75 GHz), (1.75–2 GHz) and(>2 GHz).F. DecoderThe three to eight decoder selects one-out-of-eight CPs. When all three inputs are ‘0’, thismakes B0 = 1, and when all inputs are ‘1’, thismakes B7 = 1. Bits B0–B7 energizes CPs # 1–8,respectively. The circuits were implemented usingAND, OR, INVERT logic.IV. IMPLEMENTATION ANDSIMULATIONS OF THE FLASH DPLLTo prove that the flash DPLL locks muchfaster than the conventional DPLL, both arecompared.A. Conventional DPLLFig. 6 shows part of the flash DPLL,namely the conventional DPLL. It is composed of aPFD, CP (CP#1 was used), LPF and VCO. Thisexcludes the flash portion, namely frequencycomparator, encoder, decoder and MCP.Many examples were performed in thefrequency range 300 MHz–2 GHz. To determine thelock time, the voltage (Vcntrl) from the CP wasmonitored and the input frequency (Fin) wascompared with the output frequency (Fvco). TheDPLL is considered to be locked. The phase shiftbetween Fvco and Fin becomes zero or constant.Example simulations for the frequency range 300MHz–1.8 GHz are shown in Fig. 7.Figure 6 Conventional DPLL simulation schematicFigure 7 Conventional DPLL 300 MHz–1.8 GHzHop (zoomed to view waveforms at locking)B. The flash DPLLFig. 8 shows the flash DPLL schematicused for simulations. Since we do not know whenthe input frequency hop takes place during any 20 nscycle, we actually need two 20 ns cycles, that is, 40ns; the first 20 ns cycle is needed to detect a changein Fin, whereas the second 20 ns cycle is used todecide which frequency is larger. If Fin changesagain during the second 20 ns cycle, this change willbe resolved, that is, a decision as to which frequencyFin (new) or Fref is larger, during the next 20 nscycle.Figure 8 Flash DPLL simulation schematicTo perform simulations, the frequencycomparator array was removed and replaced withVpulse signals that are manually programmed tooutput the exact signal levels per frequency hop, asthat of the frequency comparator. The reason forsuch replacement is the slow processing speed thespectra software. To simulate the frequencycomparator array, it took disproportionately longtimes, compared to the time taken by an individualfrequency comparator. Since the circuitry of thefrequency comparator array is so complicated andinvolves a great amount of parallel processing, withthe software doing thousands of calculations, thismade it difficult to obtain sufficient data, takinghours and days to run just a small percentage of thefull simulation. Thus the array of frequencycomparators was replaced by a block which merelyexhibits 40 ns delay then places the thermometercode, corresponding to the new input frequencyunder consideration (after the frequency hop), at theinput of the priority encoder. This method ofsimulation provides a reasonably good estimate ofthe DPLL lock times for different input frequencyhops.Many examples were performed in thefrequency range 300 MHz–2 GHz. Examplesimulations for the positive frequency hop of 300MHz–1.8 GHz are shown in Fig. 9; it clearly showsan input frequency hop taking place at 200 ns, which
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752751 | P a g eis followed by a conventional change of Vcntrlduring the above-mentioned 40 ns delay. At about240 ns, Vcntrl jumps steeply when the new CP isselected, thus marking the end of the coarse-tuningstage and the beginning of the fine-tuning stage; thelater stage ends with the DPLL locking at 297 ns,that is, a lock time of 97 ns.Figure 9 Flash DPLL 1.8 GHz–300 MHz Hop (hoptook place at 200 ns and Tlock = 119 ns)TABLE 3LOCK-TIME COMPARISON FOR FLASH ANDCONVENTIONALDPLLS FOR DIFFERENT FREQUENCY HOPSFrequency hopFast-lockingDPLL, nsConventionalDPLL, ns300 MHz–800MHz92 150800 MHz–1 GHz 103 2171 GHz–1.8 GHz 97 312C. Comparison tablesTable 3 provides a summary of simulationresults. It compares the fast-locking DPLL againstthe conventional DPLL; it also compares all locktimes for different values of input frequency hops.Thus, the significance of this paper’s contribution isthat it not only represents a significant advancementsince the publication of the conventional DPLLs in[1, 2], but also represents an advanced techniquewithin the new hot area of fast-locking DPLLs.V. CONCLUSIONSA novel fast-locking DPLL was designed toimprove the lock time over that of the conventionalDPLL. The fast-locking DPLL employs a flashalgorithm similar to the one employed in flash A/Dconverters, thus expecting fast response at theexpense of increased hardware. The flash DPLLoperation employs two stages: (i) a novel coarse-tuning stage comprising an array of frequencycomparators, encoder, decoder, MCPs, LPFs andVCO; during this stage the DPLL output frequencygets as close as possible to the input final frequencyin a very short time, and (ii) a fine-tuning stagecomprising a PFD, CP, LPF and the VCO; this stageresembles the operation of conventional DPLLs. Thefrequency comparator array as well as theMCP/LPFs constitute the extra hardware penaltybecause of using the flash fast-locking technique,thus there is a speed against hardware tradeoff.Design considerations for various circuitcomponents were discussed and some pertinenttesting results were provided. The entireconventional DPLL was easy to simulate. However,the entire flash DPLL was only possible to simulateafter replacing the frequency comparator array witha block that exhibits time delay and finally producesa thermometer code representing the new inputfrequency (after the frequency hop). The flash DPLLwas verified to operate in frequency range 300MHz–1.8 GHz. Table 3 demonstrates that there is asignificant improvement in the lock time by usingthe flash DPLL as opposed to the conventionalDPLL.Faster lock times of the flash fast-lockingDPLL can be achieved by including a larger array offrequency comparators composed of 16 or 32comparators; this will result in a finer coarse-tuningstage and consequently a faster fine-tuning stage. Itis thus expected that all lock times will be below the100 ns mark in the above mentioned frequencyrange.REFERENCES AMBARISH S., WAGDY M.F.: ‘A wide-band digital phase locked loop’. Proc. ThirdInt. Conf. Information Technology: NewGenerations (ITNG 2006), Las Vegas, NV,10–12 April 2006, pp. 597–598. JANARDHAN H., WAGDY M.F.: ‘Designof a 1 GHz digital PLL using 0.18 mmCMOS technology’. Proc. Third Int. Conf.Information Technology: New Generations(ITNG 2006), Las Vegas, NV, 10–12 April2006, pp. 599–600. WAGDY M.F., VAISHNAVA S.: ‘A fast-locking digital phase locked loop’. Proc.Third Int. Conf. Information Technology:New Generations (ITNG-2006), Las Vegas,NV, 10–12 April 2006, pp. 742–746. SUTTON B.P.: ‘Reduced lock time for aphase locked loop’. US Patent # 6,380,810,30 April 2002. BELLAOUAR A., SHARAF K.: ‘Fast lockself tuning VCO based PLL’. US Patent#6,566,966, 20 May 2003. DAVIS C.M., BROUGHTON D.L.,PORTER E.W.: ‘Method and circuit forimproving lock-time performance for aphase-locked loop’. US Patent # 6,624,707,23 September 2003.
Raman Bondare, Rajesh Langote / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.746-752752 | P a g e MCDONALD J.J., HULFACHOR R.B.:‘Circuitry to reduce PLL lock acquisitiontime’. US Patent # 6,940,356, 6 September2005. BAKER R.J.: ‘CMOS circuit design,layout, and simulation (IEEE Press, WileyInterscience, Piscataway, NJ, 2005, 2ndedn.), pp. 985–986. GADDE P., WAGDY M.F.: ‘A 2-GHzdigital PLL using 0.18 m CMOStechnology’. Proc. IEEE Second Int.Computer Engineering Conf. (ICENCO2006), Cairo, Egypt, 26 –28 December2006, HW 61–66. NIZAMANI A.S.: ‘A novel frequencycomparator: applications in frequencymeters and in difference clocks forgenerator frequency error monitors’, IEEETrans. Instrum. Meas., 1996, 45, (1), pp.320–323. BONDARE R.: ‘Design of High FrequencyPhase Locked Loop’. Proc. IEEE Int. Conf.on Communication Control and ComputingTechnologies (ICCCCT-2010),Ramanathapuram, Tamilnadu, 7-9 October2010, pp. 586-591.