Pratim Bhattacharjee, Ganesh Lakshmana Kumar Moganti, Dr. Susanta K Mandal /International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622www.ijera.com Vol. 3, Issue 3, May-Jun 2013, pp.642-645642 | P a g eHigh Speed-Low Leakage-Multi Threshold 45 nm Floating GatedSRAMPratim Bhattacharjee*, Ganesh Lakshmana Kumar Moganti**, Dr.Susanta K Mandal****(M.Tech. VLSI Design and Embedded System, School of Electronics Engineering. KIIT University. Odisha.INDIA)** (Associate Professor, School of Electronics Engineering. KIIT University. Odisha. INDIA)*** (Professor and Associate Dean, School of Electronics Engineering. KIIT University. Odisha. INDIA)ABSTRACTAn asymmetrically six-transistor (6T) high speedlow leakage multi Vth 45nm Floating Gated (FG)SRAM circuit is presented in this paper tosuppress the power dissipation and leakagecurrent. By using conventional external circuitry(decoder part, read-write circuitry part, voltagecontrol switch part etc.), this technique is reduceup to 83.29% power dissipation and 290.5 timesleakage current and also 2.52 times high speed in45 nm technology. For minimizing powerdissipation and leakage current, the function ofmulti Vdd and multi Vth concept are also includedin that paper. Also the total read-writearchitecture block diagram is included in thatpaper.Keywords – Floating Gate, Multi Vdd, Multi Vth,Read-Write Architecture, SRAM.1. INTRODUCTIONSelecting of suitable component, not onlythere intended task but also external and internaloperating condition as well as their operating limits(current, voltage and power) is still a big challengein modern electronic circuit design. Similarly for astandard system-on-chip (SoC) or microprocessor,leakage current takes an important role in theirmemory elements which is mainly recognized asRAM and ROM . Data mismatch, data loss,access time variation and so many other incidentsoccurs in the memory cell due to leakage current. Toincrease the speed of SoCs or microprocessors ahuge amount of high speed cache memory (datacache, address cache and translation look-asidebuffer) is required which is mainly constructed withSRAM cells. But for that the power supply, mutabledata stability, leakage current, internal heat, reducearea come into the picture together, which become aprimary challenge of SRAM cell designing.The paper is organized as follows. Section2 represents the basic of floating gated MOSFET.Conventional 6T SRAM circuit-operation is onSection 3. Proposed floating gated design and workfunction is on Section 4. Total circuit architectureand the resulting output on Section 5 and Section 6.The paper is concluded in Section 7.2. FLOATING GATED MOSFETA Floating gate MOS can be fabricated bystandard MOS transistor and register-capacitorlogic, so that resistive connection to its gate are notpresent. The electrically isolated secondary gates orinputs are implanted to the above floating gate (FG)are mainly capacitively connected to the floatinggate which is completely surrounded by highlyresistive material. So, in terms of its operation, thenumber of inputs act as floating inputs of thetransistor .Figure 1. N-channel N-input FGMOS Transistor3. CONVENTIONAL 6T SRAMThe conventional six transistor (6T) SRAMcell using multi Vth in 45 nm technology which ismainly characterized by the hold stability usingcross couple inverters during the read-writeoperation, shown in Figure 2. The design of the datastorage nodes which is directly connected with thebit-lines can accessed through the pass transistors.Voltage deviation which is mainly associated withthe cross coupled inverters and the pass transistorsbecause of the leakage current, hamper the storagenodes.Another important issue is the externalnoise, which is directly affect the read-accessmechanism, which is so called known as destructiveread of a standard 6T SRAM  and affect is read-write violation.To maintain the data stability and highspeed access the sizing (β ratio) of the cross coupledinverter transistors and the access transistors contain
Pratim Bhattacharjee, Ganesh Lakshmana Kumar Moganti, Dr. Susanta K Mandal /International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622www.ijera.com Vol. 3, Issue 3, May-Jun 2013, pp.642-645643 | P a g ea big role . For maintaining the read and writestability the cross coupled transistors M1 and M3 (forread) and M2 and M4 (for write) must be stronger ascompared to the access transistors M5 and M6. But incase of the low leakage purpose in 45 nmtechnology the Vth of the M5 and M6 must be higherthan the access transistors M1, M2, M3, and M4.Figure 2. Conventional 6T SRAM cell (M5and M6High_Vth and M1,M2,M3,M4 Normal Vth)Normally BL and BLB are precharged byVdd_Low when the particular SRAM address is notselected. In both read-write operations the accesstransistors M5 and M6 are in saturation mode. Forwrite „1‟, BL must be 1 and BLB must be 0, becauseof WL is high the transistor M5 and M6 are on andfor that M2 and M3 are on and Vdd value is appearedinto node A. For read operation, the stored valuefrom node A goes to the BL and node B goes to theBLB and sense amplifier sense the value. In case ofzero (0) the opposite phenomena will occur .4. PROPOSED MULTI VTH FLOATINGGATED SRAMIn the proposed work of the paper there aretwo input NFGMOS and PFGMOS areimplemented. The cross coupled inverters arereplaced by PFGMOS and NFGMOS.One of the inputs of both FG_MOSs isbiased mode for tuning the MOS (Vth) (basicallyhear I use positive bias voltage for NFGMOS andsame negative bias voltage for PFGMOS) andanother input is used as operational input. Thedesign of the proposed circuit is typicallycharacterized by the ratio (β) of the size of the pull-down transistors to the access transistors.Precharged case and the read-writeoperation are similar as the conventional 6T SRAMcircuitry. For write zero (0) BL must be zero andBLB must be one which is controlled by the holecircuitry which is mention in the block diagram lateron. For the high gate voltage (WL high) the accesstransistor are on and for that M1 and M4 are on andthe node A value is grounded, so zero is stored onnode A and node B stored the opposite one.Figure 3. Six transistor (6T) Multi Vdd AND MultiVth Floating Gated SRAM (M5and M6 High_Vthand M1,M2,M3,M4 Low_Vth and M7 Low Vth andM8 High_Vth)For read operation, the stored value fromnode A goes to the BL and node B goes to the BLBand sense amplifier sense the value. In case of one(1) the opposite phenomena will occur. Comparisonof the both cases with the conventional 6T SRAMoperation 83.29% power dissipation is reduced aswell as speed is increased by 2.52 times for highcurrent flow. The row wise virtual groundmechanism using inverting circuit (βn > βp) willalso reduce the leakage current up to 290.5 times, itis because there are no option for grounding of themain circuit.5. TOTAL CIRCUIT ARCHITECTUREThe total circuit apart from SRAM cellarray there are sense amplifier and write driverwhich are work together as read-write circuitry, rowdecoder and column decoder both for addresslocation, write enable and bit line voltage levelswitch are work together as multi Vdd  (Vdd_Highand Vdd_Low).For a particular SRAM which address isselected by the decoder section is used onlyVdd_High and rest of SRAM array are controlled byVdd_Low of power consumption of the wholearchitecture. Based on CD (column decoder) thecircuit will precharged (CD=1) or enable for read-right operation (CD=0). When CD=0, the rowdecoder will activate and put high signal for desireSRAM row (word line) for operating particularSRAM (1Bit). At that time the by data in pinprocessor will store its desire data to the wholeSRAM array.
Pratim Bhattacharjee, Ganesh Lakshmana Kumar Moganti, Dr. Susanta K Mandal /International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622www.ijera.com Vol. 3, Issue 3, May-Jun 2013, pp.642-645644 | P a g eFigure 4. Block diagram representation of totalcircuit architecture6. SIMULATION RESULTSThe simulation result of the total circuitusing conventional 6T SRAM and 6T Floating GateSRAM is shown in Figure 5 and Figure 6.It is clear from the output graph that the read andwrite operation is only done while particular addressis selected by the microprocessor.Figure 5. Total circuit output graph (conventional6T SRAM) (Transient analysis time=0s – 600ns)(En: Enable , when „0‟ sense amp. will on and when„1‟ write driver will on and opposite case they are inoff state, OUT represent the read write operation of1 Bit conventional SRAM)WE (Write enable) enable the total circuit.Based on CD (column decoder) the circuit willprecharged (CD=1) or enable for read-rightoperation (CD=0).When CD=0, the row decoder will activate and puthigh signal for desire SRAM row (word line) foroperating particular SRAM (1Bit). In the both graphit is clearly visible that data in line is both 0 or 1 andaccordingly write driver write it into the SRAM andsense amplifier sense it, which is plotted on OUTline.Figure 6. Total circuit output graph (6T FloatingGate SRAM)(Transient analysis time=0s – 600ns) )(En: Enable , when „0‟ sense amp. will on and when„1‟ write driver will on and opposite case they are inoff state, OUT represent the read write operation of1 Bit conventional SRAM)6.1 Power DissipationApart from the SRAM cells the total circuitof conventional 6T SRAM and proposed SRAM areproperly working at 980 mV.Figure 7. Graphical representation of powerdissipation of conventional circuit (transientanalysis time=0s – 600ns)But the average power dissipation usingmulti Vdd and multi Vth is drastically reduce up to83.29% using the proposed technique, whereconventional SRAM work at minimum of 980 mVas well as proposed SRAM at 320 mV.Figure 8. Graphical representation of powerdissipation of proposed circuit (transient analysistime=0s – 600ns)6.2 Read-Write SpeedSRAMs hold data that is frequentlyaccessed by the processor. The faster the access, thefaster the data transfer from SRAM to CPU. The
Pratim Bhattacharjee, Ganesh Lakshmana Kumar Moganti, Dr. Susanta K Mandal /International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622www.ijera.com Vol. 3, Issue 3, May-Jun 2013, pp.642-645645 | P a g edata fetching and writing speed is depending onread-write circuitry and SRAM array combined. Asfar our calculation from delay calculator we foundproposed SRAM circuitry is 2.52 times faster thanconventional SRAM circuitry.6.3 Leakage currentComputer memory which does not requirerefresh operation is SRAM. But in case of hold datait has some leakage current which is very lesscompare to the other computer memory.Figure 9. Graphical representation of leakagecurrent of conventional circuit (transientanalysis time=0s – 300ns)The stability of a particular SRAM isinversely proportional of the leakage current. So theproposed SRAM is very much stable (290.5 times)compare to the conventional SRAM because of itslow leakage current.Figure 10. Graphical representation of leakagecurrent of proposed circuit (transient analysistime=0s – 300ns)Table 1. Performance Comparison of differentSRAM circuitsOperation1BitConventional6T SRAM1Bit 6TFloating GatedSRAMOperatingVoltage980 mV 320mVTotal CircuitOperatingVoltage980 mV 980 mVTotal CircuitAvg. PowerDissipation36.23E-6 W 6.055E-6 WRead- writeoperation time0.78 ns 0.31 nsLeakageCurrent550 nA 1.893 nA7. CONCLUSIONHigh speed low leakage multi threshold45nm floating gated SRAM which will reduce theactive and standby mode power dissipation as wellas enhancing the data stability and read-write modeas well as hold time leakage current and increasingthe read-wright speed is proposed in this paper. Upto 83.29% power saving and 2.52 time faster speedand 290.5 time more stability are achieved with theproposed floating gated SRAM as compare to theconventional design. The above circuit design andsimulation is on Cadence Virtuoso environment.ACKNOWLEDGEMENTFirst of all I would like to thank both of myguide G.L.Kumar Moganti and Dr. S.K.Mandal forguiding me throughout the research part.I am also grateful to my friends LopamudraPattanayak, Abhinab Anand, Srijan Chattacharjeeand Pratik Ganguly for all their helping handsduring my days of research.I am also thankful to all the staffs andemployees of School of Electronics Engineering ofKIIT University.REFERENCES Dr.Esther Rodriguez-Villegas, “Low Powerand Low Voltage Circuit Design withFGMOS Transistor” - IET Circuits,Devices and Systems Series 20. Sung-Mo Kang and Yusuf Leblebici,“CMOS DIGITAL NTEGRATEDCIRCUITS Analysis and Design”. V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, John Wiley& Sons Ltd., 2006. S.Rusu, S. Tam, H. Muljono, D. Ayers, J.Chang, B Cherkauer, J.Stinson, J. Benoit,R. Varada, J. Leung, R. D. Limaye, and S.Vora, “A 65-nm dual-core multithreadedXeon processor with 16-MB L3 cache,”IEEE Journal of Solid-State Circuits, Vol.42, No. 4, pp. 846-852, April 2007. Z. Liu and V. Kursun, “High Read Stabilityand Low Leakage Cache Memory Cell,”Proceedings of the IEEE Symposium onCircuits and Systems, pp. 2774-2777, May2007. L.Chang et al., “Stable SRAM Cell Designfor the 32 nm Node and Beyond,”Proceedings of the IEEE SymposiumonVLSI Technology, pp. 128-2129, May 2005.