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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

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  1. 1. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362356 | P a g eµPCBComplexityGollapudi Ramya, M.Anil KumarDepartment of Electronics and communication Engineering, K.L.University, VaddeswaramProfessorDepartment of Electronics and communication Engineering, K.L.University, VaddeswaramABSTRACTSystem design complexity is increasingrapidly. As a result current development costscan be staggering and are constantly increasing.As designers produce ever larger and morecomplex systems, it is becoming increasinglydifficult to estimate how much time it will take todesign and verify these designs. To compoundthis problem, system design cost estimation stilldoes not have a quantitative approach. Althoughdesigning a system is very resource consuming,there is little work invested in measuring,understanding, and estimating the effortrequired.To address part of the currentshortcomings, this paper introducesµPCBComplexity, a methodology to measure andestimate PCB (printed circuit board) designeffort. PCBs are the central component of anysystem and can require large amounts ofresources to properly design and verify.µPCBComplexity consists of two main parts, aprocedure to account for the contributions of thedifferent elements in the design, which is coupledwith a non-linear statistical regression ofexperimental measures. We use µPCBComplexityto evaluate a series of design effort estimators onseveral PCB designs. By using the proposedµPCBComplexity metric, designers can estimatePCB design effort.1 IntroductionPrinted circuit board (PCB) design effortkeeps growing as additional constraints such asrising clock frequencies, reduced area, increasingnumber of layers, mixed signal devices, and the everincrease in component numbers and densities. All ofthese factors combined have led to a steady rate ofincrease in development costs for current systems.As we design ever larger, denser and more complexsystems, it is becoming increasingly difficult toestimate how much time would be required todesign and verify them. To compound this problem,PCB design effort estimation still does not have aquantitative approach. We present in this paper afirst step toward creating a design effort metric thatis highly correlated with design effort forPCBlayout. We follow the same approach taken in [1] asthe principles that are applicable to microprocessorsare also applicable to PCBs. In this paper, designeffort corresponds to the number of engineering-hours required for implementation (layout) of a PCBdesign.This paper analyzes and proposes variousstatistics to estimate the layout effort required todevelop PCBs. We investigate and quantify statisticssuch as area, component count, pin count and devicetypes and sizes for many PCBs. We analyze severalof these statistics, and propose a metric, obtainedafter applying non-linear regression over thedifferent statistics, which we call µPCBComplexity.In addition, we provide insights on the correlationbetween several statistics and design effort forseveral known layout design times.Different designs have differentconstraints, leading to specific challenges; typicaldesign constraints being area, frequency, and cost.For example, having area being a primary designconstraint, may lead to a requirement for additionallayers, more expensive package types, and morecomplex placement and routing. A designconstrained by cost, on the other hand, may requirea balance between number of layers, area, drilldensity, types of packages and possibly the numberof different drill sizes. Having clear constraints isnecessary in estimating layout effort as it candrastically affect complexity.We define design effort to be the layouttime required by one engineer. Design effort isequivalent to layout time when the project has asingle developer, which is frequent even forcomplex PCBs. Nevertheless, for a given effortrequirement, it is possible to reduce the design timeby increasing the number of workers. Nevertheless,increasing the number of workers decreases theproductivity per worker. The relationship betweenthese two elements has been widely studied insoftware metrics and business models. Since theconversion between design effort and design timecan be approximated, the remainder of this paperfocuses only on design effort.The rest of the paper is organized asfollows. Section 2 covers other work in this area;Section 3 describesthe statistical techniques thatallow us to calibrate and evaluate theµPCBComplexity regression model; Section 4describes the setup for our evaluation; Section 5evaluates several statistics for the boards in ouranalysis; and Section 6 presents conclusions andfuture work.
  2. 2. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362357 | P a g e2 Related WorkThe capability to rapidly develop complexPCBs is a tremendous competitive advantage, sincehigh development productivity is essential for thesuccess of any design team. Although somecompanies have used statistical methods to estimatePCB design time, those methods are consideredtrade secrets [9]. Other companies do not releasedetails because they provide competitive advantageover other companies. As a result, we are unawareof any published work on the topic of predicting theengineering hours required for a PCB design.[1] focuses on microprocessor design effort. Whilethe work described in this paper focuses on PCBdesign metrics, [1] uses the same regression model,but both papers analyze different set of statistics andtargets.Another paper that looks at productivity is [7] whichidentifies the need for standards or infrastructuresfor measuring and recording the semiconductordesign process. They propose improving designtechnology, time-to-market, and quality-of-result byaddressing the Design Productivity Gap and theDesign ‖Technology‖ Productivity Gap. However,this previous work focused mostly on the problemsassociated with the infrastructure and design toolsrelated to the physical implementation ofsemiconductor designs, while the focus of this paperis layout effort associated with PCB designs.In [8] a factor similar to the productivity factor isdescribed. They use the ―process productivityparameter‖ to tune the estimating process forsoftware projects. They contend that if you know thesize, time, and the process productivity parameteryou can use it to make estimates for a new project.So long as the environment, tools, methods,practices, and skills of the people have not changeddramatically from one project to the next.Much research has been done in Design forManufacturing (DFM) and Design for Production(DFP) which seek to improve the production andmanufacturing times of PCB assemblies. This paperseeks to develop a metric that can aid in predictingthe layout effort, based on analysis of characteristicsof PCBs at a low-level so as to better plan for futuregenerations of systems. In [2] the issue of embeddedpassive components is discussed as a necessity tothe smaller electronic devices requiring ever smallerPCBs. They note that board area is becoming socritical thatto keep pace with the size constraintsnew techniques are required. Our goal would be toeventually develop a set of metrics and a model thatestimates design effort by also taking into accountmanufacturing times.3 ApproachOur goal is to develop a quantitativeapproach and to have a model that quickly estimatesdesign effort based on several easily gatheredstatistics. This is important because being able topredict design effort is advantageous in helping toreduce design costs. To build the model, we analyzemany commercial computer/electronic devices andgather data from the PCBs within. The layout timesfor these PCBs were well documented which was arequirement for this analysis. Table 1 lists thecritical components of PCB designs as determinedby [2]. These parameters contribute to thecomplexity of a design, and hence the time requiredto do layout.Some design parameters listed in Table 1are dependent on other factors. For example, thesize of the board is defined by the number ofembedded and discrete passive components andtotal wiring requirements. However, the total wiringrequirements are governed by the number ofembedded and discrete passive components in thePCB. And furthermore, the total number of layers inthe PCB depends on the size of the board, thenumber of embedded and discrete resistors andbypass capacitors [2].1. Board dimensions (length and breadth)2. Total wiring requirements3. Number of layers4. Number of embedded resistors (if used)5. Number of embedded capacitors (ifused)6. Set of active component types and theirnumber7. Thickness of the board8. Number of discrete resistors9. Number of discrete capacitorsTable 1: Critical design parameters for a PCBThese critical design parameters arefocused towards manufacturing ability, not designeffort estimation. We used them as a starting pointin determining what parameters or metrics toanalyze and include for correlation with designeffort. None of the boards in our study haveembedded passive components, instead we focus onthe total number of all components (passive anddiscrete) and the pin count for them. These areeasily obtainable values.Since the routing data is not easilyobtainable, the number of pins for all thecomponents in the design are taken into accountinstead. While this is not an ideal metric since notall pins are used or have very short traces (VDD orGND), it is readily obtainable an does not hamper
  3. 3. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362358 | P a g ethe focus of this paper, namely effort predictionstarting from higher level design descriptions, suchas a bill of materials (BOM) or schematics.In order to find a metric highly correlatedwith design effort, several statistics were gatheredfrom the existing designs. For each isolated boardwith a known design effort, we look at severalstatistics and apply non-linear regression to find ahighly correlated metric.We present our design effort model as theaggregate of a set of statistics (Si). Each of whichhas a specific constant (wi), associated with it,which assigns a weight to the importance of everystatistic used as input in the model. The aggregate ofthe statistics is inversely proportional to theproductivity of a specific design team which isrepresented by a constant (ρ). The model ispresented in Equation 1. In order to find suitablevalues for each of the data weights (wi) we performmixed non-linear regressions on this equation. Thedesign team productivity factor (ρ) is constant perdesign group, and it needs to be adjusted on a percompany or design team basis. If the ρ is unknown,then the absolute design effort is invalid and onlythe breakdown inside the project is correct.Obtaining the value of ρ is simple; all that is neededis to have the design effort for a single project.Alternatively, it is possible to develop a productivitybenchmark suite that calibrates ρ for a givencompany.(1)In order to determine the weights that givea generalized solution to Equation 1, [1] proposes touse a mixed non-linear regression model. If there areno productivity adjustments, it is possible to use asimpler non-linear regression model. While the sumof a large number of random variables is distributednormally, the product of a number of randomvariables is distributed lognormally — a distributionwhere the logarithm of the variable is normallydistributed [4]. Therefore, since the randomvariables have a log normal distribution an evensimpler linear regression model can not be used.To evaluate the accuracy of the model(Section 5), we use σ as a measure of errorassociated with the fit. Consequently, it is importantto understand what different values of σ tell us aboutthe quality of the estimate. For a given σ, we canfind a confidence interval for the estimated effort.The x% confidence interval for a metric is definedto be the range of efforts (Estimatelow, Estimatehigh)such that P (Estimatelow < metric prediction <Estimatehigh) = x/100. For example, the 90%confidence interval gives us two values a and b suchthat there is a 90% chance that the actual effort isbetween metric prediction × a and metric prediction× b.3.1 Productivity AdjustmentsIn software development projects, it is wellknown that different development teams havedifferent productivities. For example, it has beenshown that the productivity difference betweenteams can be up to an order of magnitude [5]. Webelieve that a similar effect occurs between PCBdesign teams. The productivity differences may bedue to multiple factors, including the averageexperience of the designers in the team and the toolsused. In our model, ρ captures this effect.The boards under study in this analysis allcome from one manufacturer and so the use of aproductivity factor was not necessary.3.2 Team Size DynamicsAlthough some board designs require longperiods of time, it is very rare to find multipledevelopers doing different sections of the sameboard. The PCB layout effort by nature is a lineartask done by one engineer at a time. To reduce thedesign time, we have found two approaches: multi-timezone working environments, and ‖surgical‖teams.A multi-timezone team has differentdesigners working on multiple time zones, this is,once a designer stops working a new designer cancontinue and pick up where the previous designerleft. A ―surgical team‖ [6] follows an alternativedesign organization, with the surgeon, or chiefdesigner, at the helm and a supporting staff that hastheir tasks allocated by the chief of staff. In the PCBcase, we may have other designers doing such tasksas making footprint images for components, whichcan be a tedious effort.We gathered data from a number of PCBdesigns for the analysis done in this paper. Table 3shows the types of statistics gathered for each of theboards analyzed. When calculating the areaconsumed for each component we did not considerthe cases where routing, or in the more rare caseplacement, could be done underneath a component.Several board designers pointed out that thecomponent and pin density of the board was one ofthe crucial factors to estimating design effort. Tocapture component and pin density, we define themwith equation 2 and equation 3 respectively.nkkk SwEffortDesign1)*(*1(2)componentsw/Sides#*Area#DensityComponentPCBcomponents(3)Area)(PCBPins#Density Pin
  4. 4. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362359 | P a g e4 Evaluation SetupTable 2 gives a description of the boardsalong with the engineering notes that we were ableto gather from the de-signers. Boards B7-B11 usedSPECCTRA for OrCAD which is a commonautorouter used in industry. No data was availableon the use of an autorouter for boards B1-B6 but itcan be safely assumed that some autoroute tool wasused.In discussions with the designer of boards B8 andB9 the size of the LCD in the system dictated thesize of the PCB and the housing that contained it.The LCD was counted as aTable 2: Description of boards analyzedTable 3: Description of the statistics gathered fromthe PCBscomponent in our analysis and took one completeside of both these boards, forcing the placement androuting of all other components to one side. Costwas the main consideration for both these boardsalso and this forced the designer to route everythingusing only 2 layers.Among boards B7 through B11 the smallestboard, B10, was judged to be the most difficult tolayout. Where as boards B7 and B11 were theeasiest. This was attributed to the ar-eas available todo the placement and routing. B7 and B11 were twoof the largest boards reviewed and they were notarea constrained, this gives much latitude to thedesigner for placement and makes the autorouterproduce better results. With a more constrained areamore human intervention is re-quired during therouting phase which was the case for B10.For the placement stage we only had to considerthe number of sides of the board on whichcomponents were mounted. Most of the boards inthis study had the components all on one side,though a few had bypass capacitors mounted on oneside, which accounted for a negligible amount ofspace. Again, through-hole devices would effect theavailable placement area as it did the availablerouting area as space would be lost on both sides ofthe board, unlike with surface mounted components.This was not a factor in this study since most boardsonly used one side for placement. Boards B8 and B9had components on both sides but one side wasBoard Description Engineering NotesB1 Signal ConditioningMany thru-hole components. Analog board with manyimportant signal pathsB2 AE RMSMany thru-hole components. Analog board with manyimportant signal pathsB3 PMD Motor Controller Many high density componentsB4 Motor Driver New footprintsB5 Enviro Controller Forgot reasons why it took so longB6 Current SourceMany components on a small board. MechanicalconstraintsB7Arbitrary WaveformGenerator/Amplifier Placement constraints due to noise reductionB8 ACDC MonitorCost major factor. Time consuming to keep to a 2layer boardB9 Tank MonitorCost major factor. Time consuming to keep to a 2layer boardB10 Air spring remote Very small. RF constraintsB11 Air Spring Controller 2 Isolated grounds with placement constraintsBoard Statistic Board StatisticPCB Size (mm2) Physical size of the PCB# of Sides w/ Comp Either 1 or 2 sides has components# of Routing Layers Layers used for routing traces# of LayersThe total number of layers in thePCBComponents# Passive Passive components (resistors. . . )# Digital Digital integrated circuits (IC)# Analog Analog ICs or devices (opamps. . . )# Mixed SignalICs with both digital and analogsectionsTotal #Total count of all components onPCBTotal Area (mm2) Total area of all components on PCBDensity Ratio of component area to areaPins# Passive Pins for all passive components# Digital Pins for all digital components# Analog Pins for all analog components# Mixed Signal Pins for all mixed signal componentsTotal Pins for all devices on PCBDensity Ratio of number of pins to area
  5. 5. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362360 | P a g epopulated by only one component, the LCD. BoardB10, the only other board with components on bothsides, did not have any through-hole devicespresent.5 EvaluationOur evaluation analyzes 11 different printed circuitboards. Table 4 shows the main results andcharacteristics for each of these. The first columncorresponds to each of the statistics or metricspresented in Table 3 (Section 4). Columns B1 toB11 correspond to each of the boards (Table 2). Thelast column corresponds to the σ between the rowand design effort. Since all the boards are designedby the same team, we do not evaluate theproductivity factor (ρ).B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 σDesign Effort (hours) 68 35 43 21 48 48 24 40 32 24 12 0Components# Passive 213 165 101 80 108 222 116 86 83 19 47 0.52# Digital 15 0 17 0 8 2 0 11 8 4 4 0.99# Analog 24 24 1 10 24 50 28 4 16 1 11 1.10# Mixed Signal 11 0 7 0 0 3 0 0 0 0 0 0.75Total # 263 189 126 90 140 277 144 101 107 24 62 0.51Total Area (mm2) 6214 9053 6964 2719 9144 6579 8104 12193 12296 777 5430 0.93PinsPassive 563 429 365 182 414 578 414 194 188 39 109 0.62Digital 154 0 518 0 107 32 0 175 173 88 32 2.18Analog 188 208 8 98 72 400 150 25 53 14 65 1.19Mixed Signal 172 0 208 0 0 48 0 0 0 0 0 2.00Total 1077 637 1099 280 593 1058 564 394 414 141 206 0.43PCB Size (mm2) 22194 22194 22194 16258 38710 20452 22194 10968 10968 1277 25548 0.52# of Sides w/ Comp 1 1 1 1 1 1 1 2 2 2 1 3.17# of Routing Layers 2 2 3 2 2 2 3 2 2 4 2 1.18# of Layers 4 4 6 4 4 4 4 2 2 4 2 0.94Component Density(x1000) 62 45 30 29 19 71 34 24 26 49 13 0.48Pin Density 50 30 51 18 16 54 26 37 39 115 8 0.64µPCBComplexity(hours) 60 44 44 16 37 57 32 35 33 24 13 0.2Table 4: Statistics, design effort, and correlation results of study boards.This simplifies the analysis, and we can use non-linear regression instead of the mixed-effects non-linear regression model. With σ we can compute theconfidence interval. For the lognormal distributionused, the mapping between σ and the 90%confidence interval is shown in Figure 1. We willuse this chart to compare the ac-curacy of differentestimators.Factor4PCBComplexityComponents3.53PinsMultiplicative2.521.590% Conf10.500.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8σFigure 1: Mapping between the standarddeviation of the error (σ) and the 90%
  6. 6. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362361 | P a g econfidence interval for the lognormal errordistribution used.The design effort values were obtained byinterviewing the original designers. Obviously, thereis perfect correlation with itself so σ = 0. A zero σresults in a perfect (1, 1) confidence interval. Wenow proceed to analyze easily available statisticslike number of components and pin count. Thesetwo sets of statistics are easily available before thePCB design starts. They are part of the PCBspecification.From the boards analyzed, we observe that it isbest touse the total number of components toestimate design effort (σ = 0.51).Although traces for analog components and digitalcomponents are more difficult than traces forpassive components, the low amount of digitaland/or analog components on several of the boardsmake it difficult to use them as a method to estimateeffort. Figure 1 shows the confidence interval for a σ= 0.51 as the intersection between the componentsline and the confidence interval line (0.43, 2.31).This means that using the number of components onthe specification, we have a 90% confidence that thedesign effort would be between 0.43 and 2.31 timesthe prediction.Statistics about the pins are as easilyavailable as components even before the designstarts. The number of pins is an even better predictor(σ = 0.43) than the number of components (σ =0.51). The resulting 90% confidence interval for thenumber of pins is (0.49, 2.03). This means that justby using the pins, we have a 90% confidence thatthe prediction is roughly half or double the expecteddesign effort. Not shown in the table is the result ofcombining the number of pins and the componentsto predict design effort.The results did not improvebecause there is a high correlation between pins andcomponents.Area is an interesting statistic. Just byknowing the final dimension of the board, we canestimate design effort with a (0.43, 2.35) confidenceinterval. This is roughly the same accuracy as thenumber of components. The reason is that PCBs arealways area constrained . If the specificationprovides a realistic area constraint, it could be agood way to estimate design effort. Table 4 alsoshows other statistics such as number of sides used,routing layers, and number of layers. Those statisticsare not so useful by themselves because they arehighly quantized, and this makes them difficult touse to predict effort.The proposed µPCBComplexity metrics are nowevaluated.To obtain µPCBComplexity shown inTable 4, we analyzed multiple combinations ofparameters and followed suggestions fromexperienced board designers. The best resultswere achieved when using the followingequation:Effort ∝ # Passive Comp.+ Comp.Density + PinDensity(4)Section 4 explains how to computecomponent density and pin density. To obtainthe factors on equation 4, we perform non-linear regression as explained in Section 3.Although neither pin nor component density canachieve better predictions than the number ofpins, when integrated together in theµPCBComplexity metric we achieve a 0.2 σ. AsFigure 1 shows, this represents a (0.72, 1.39)confidence interval. This roughly means that byusing the proposed µPCBComplexity metrics,with a 90% confidence designers can predictdesign effort with less than 40% error.Figure 2 shows a scatter-gather plotbetween design effort and our µPCBComplexitymetric. This is an intuitive way to see that there is ahigh correlation between design effort and themetric proposed.µPCBComplexity works well because PCBdesign complexity increases as the component andpin density increases. Designers can increase thenumber of layers on the PCB to decrease the pindensity or increase the area to reduce both densities.The problem is that both approaches require morecostly boards. As a result, designers trade-offbetween time to market and density.6 Conclusions & Future WorkThe goal of this paper was to explore thecorrelation of some easily obtained metrics of aPCB and see which were most correlated to thedesign effort required during the layout stage ofdevelopment. Many simplifications were made; wedid not account for traces of differing sizes, we didnot look at hole sizes or density, the frequency ofthe boards were not considered, nor the extraconsiderations required for analog noise filtering.Also, we need additional PCBs from morecompanies with teams of differing sizes to develop amore general model for predicting design effort.Many factors and constraints effect thedesign effort re-quired for a board to be successfullyplaced and routed. Some difficulty metric would behelpful but guidelines need to be established asdifficulty is a very subjective term. Being able toanalysis different options for a board would beuseful, such as being able to change the size of theboard to see what effect it would have on theestimated design effort. This could be expanded toalso include the number of layers since this wouldease routing congestion.
  7. 7. Gollapudi Ramya, M.Anil Kumar / International Journal of Engineering Research andApplications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.356-362362 | P a g e70●60Effort50● ●40●●●Design30●● ●20●10●00 10 20 30 40 50 60 70uPCBComplexityFigure 2: Scatter-gather plot of design effort vs.PCB metricWe see this initial research leading intomore areas of study in PCB design optimization andanalysis. We are currently analyzing data fromadditional PCB designs from different sources.These new designs have more components, morelayers, higher frequencies, and more power plains.This will give us additional metrics to add to ourmodel for possible better correlation to designeffort. These designs also have more designers onthe team which will necessitate some team orcompany productivity factor.We have extended the previously proposedµComplexity models [1] to the PCB domain. Weplan to apply the model to a number of classes atUCSC that do board development to give designguidelines to students and further refine ourapproach. Our model and metrics will eventually beavailable to researchers and industry for use inscheduling and planning PCB projects.The evaluation shows that a simplestatistics like PCB area size and number ofcomponents yield some correlation with designeffort. With a 90% confidence, area has a (0.432.35) confidence interval. This means that roughlyby looking at any of those statistics the typicaldesign time error is half/double with a 90%confidence. Much better results can be achievedwith the proposed µPCBComplexity metric. In thatcase the confidence interval for a 90% confidence is(0.72 1.39). This roughly means that less than 40%estimation error is done with a 90% confidence.Despite the good results, we still believethat much work needs to be done in gatheringrelevant designs to evaluate (with associated knowndesign times) and to refine the metrics and models.A major goal would be a rule of thumb typeequation that given some easily obtainable designparameters an accurate estimator of design timewould be generated.REFERENCES[1] C. Bazeghi, F. Mesa-Martinez, and J.Renau. µComplexity: Estimating ProcessorDesign Effort. In International Sympo-siumon Microarchitecture, Nov 2005.[2] M. Chincholkar and J. Herrmann.Modeling the impact of embeddingpassives on manufacturing systemperformance. September 2002.[3] J. Cohen. Statistical Power Analysis for theBehavioral Sci-ences. Lawrence Erlbaum,1988.[4] E.L. Crow and K. Shimizu. LognormalDistributions: Theory and Application.Dekker, 1988.[5] T. DeMarco and T. Lister. PeoplewareProductive Projects and Teams. DorsetHouse Publishing, 1999.[6] JR. Frederick P. Brooks. The MythicalMan-Month. Addison-Wesley, 1995.[7] A. B. Kahng. Design technologyproductivity in the dsm era (invited talk).In Conference on Asia South PacificDesign Au-tomation, pages 443–448. ACMPress, 2001.[8] L. H. Putnam and W. Myers. Five CoreMetrics: The Intelli-gence BehindSuccessful Software Management. DorsetHouse Publishing, May 2003.[9] Numetrics Management Systems. DesignComplexity and Pro-ductivity. Technicalreport, Numetrics Management Systems,Inc., 2004.[10] The R Development Core Team. The RReference Manual - Base Package.Network Theory Limited, 2005.