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  1. 1. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 A Comparative Study Of Matlab Results And Vhdl Analysis Of DWT For Efficient Power Systems 1* Meha Sharma, 2Rewa Sharma 1* Asst.Prof., School of Engineering and Technology,Ansal University,Gurgaon 2 Lecturer, School of Engineering and Technology,Ansal University,GurgaonABSTRACT Power Quality is one of the primary neutral current (oscillograms take at reduced andconcerns of the utilities, since lack of quality in full voltage). A minor difference between thepower may cause malfunctions, instability, short compared oscillogram can be inductive of inter-turnlifetime and so on. The efficiency and failure, which disqualifies a large and expensivesustainability of a power system is highly transformer. But impulse test could not detect minordependent on the maintenance of good quality of faults since high voltage impulse generator producespower supply. Conventional Methods have been a slightly different impulse waveform at the full andused to analyze the transient effects but found to reduced levels. This inturn will cause a differencebe high resource consuming under remote between the compared neutral current oscillogram,applications. In this aspect the Discrete Wavelet which, according to the existing standards may beTransformation (DWT) analysis has gained interpreted as a transformer fault. Another drawbackreputation of being a very effective and efficient of the recent test is the rather crude evaluation of theanalysis tool. VHDL is used to implement DWT chopped impulse test. Actually this is the mostarchitecture for improving the efficiency of critical test for the HV terminal section of theestimation and response in the power systems. winding, because of the steepness and amplitude ofThe evaluations are compared with theoretical the applied voltage. Neutral current comparison isresults from MATLAB and were observed to be not applicable here since the time to chop cannot bemeeting the accuracy of estimation. controlled. Consequently successive oscillogram of the neutral current may show a considerableKey words: DWT, VHDL, MATLAB, Power difference due to the scatter in the chopped impulseSystems, Digital Modeling duration.1. INTRODUCTION In this aspect, the wavelet analysis has The electric power requirement is gained the reputation of being very effective andincreasing due to increase in demand from electrical efficient signal analysis tool. Wavelet analysis isutilities. Since power system is AC in nature, the capable of retrieving features of data includingpower transformer is commanded as one of the most trends, breakdown points, discontinuities and selfimportant equipments in power system. Detecting similarities.minor faults in power transformer has become oneof the most important requirements for extending 2. DISCRETE WAVELETthe power quality of the power system. In recent TRANSFORMATIONyears power quality is one of the primary concerns In order to detect the minor faults(2) on theof the utilities, since lack of quality in power may transformer winding, DWT is proposed due to it‟scause malfunctions, instability, short lifetime, and time and frequency localization property. The DWTso on. In past ten years it is observed that the most is one of the three forms of WT .It moves a timeimportant causes which take the responsibility for domain discretized signal into it‟s correspondingthe power system failures and transformer damages wavelet domain. This is done through a processare the transformer winding deformations. called “sub-band decomposition” performed using digital filter banks. Therefore to safe guard the quality ofpower it is required to check whether the strength of For a given electrical signal f(n) thethe insulation of the winding can withstand for spectral bands decomposition (3)is carried out usingsevere faults. The withstanding capability of the successive decomposition of signal via pair of Highinsulation can be checked by impulse test. The pass and Low pass filter as illustrated in Fig.1.standard method of impulse testing of high voltagepower transformer is associated with the problemsregarding identification of minute failuresparticularly inter- turn faults. The(1) conventionalmethod of impulse testing of transformer is basedon the comparison of the applied voltage and the 276 | P a g e
  2. 2. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 This resolutional decomposition provides the variations, which are in spectral domain and are not available in spatial domain. These variations can result in more accurate estimation as compared to spatial estimation. To perform this decomposition in real time application filter bank architectures are realized using filter chips (or) DSP processors (5). Both the approaches provide resolutional information but are large area covering, high power consuming and slower in response due to delay in data transfer . The delay in response delay may result in improper operation of electrical controlFig.1–Sub-band decomposition scheme of a signal device resulting in lowering of life-cycle for costly and reliable electrical equipments. Basically, the DWT evaluation has twostages. The first consists on the wavelet coefficients To reduce the above difficulties associateddetermination. These coefficients represent the with the traditional DSP Processors or filter chips, itgiven signal in the wavelet domain. From these is proposed filled programmable Gate Arrayscoefficients, the second stage is achieved with the (FPGA). Technology which offers the potential ofcalculation of both the approximated and the designing high performance system at low cost.detailed version of the original signal, in differentlevels of resolutions, in the time domain. At the end 3. DIGITAL MODELING OF DWTof the first level of the signal decomposition, the For the realization of the stated DWTresulting vectors yh(k) and yg(k)will be, architecture, the filter bank architecture is developedrespectively, the level 1 wavelet coefficients of using VHDL coding. The design architecture is asdetail and approximation coefficient. shown in figure 3. The discretized(6) current pulse is In a similar fashion the calculation of the passed as input to this system in 16 bit floatingapproximated(4) (cA2(n)) and the detailed (cD2(n)) represented in excess-7 notation. The samples areversion associated to the level 2 is based on the buffered into the input FIFO of 16 x 16 location andlevel 1 wavelet coefficient of approximation are passed to the filter bank via buffer logic. The(cA1(n)). The process goes on, always adopting the inputs are off-centered by two and are passed as a“n-1” wavelet coefficient of approximation to block of 4 samples per cycle. These samples arecalculate the “n” approximated and detailed wavelet buffered into the buffer logic and are passed to thecoefficients. Once all the wavelet coefficients are filter bank on request generation. A pair of Highknown, the discrete wavelet transform in the time pass and a Low pass filter bank is realized for eachdomain can be determined. level of decomposition. Figure 2 shows the spectral decomposition Hof a secondary side output for power transformerand the decomposed detail and approximated Pcoefficients.The spectral bands provide the information ofdisturbances or variable frequency content for the Sgiven signal based on which the level of distortion Fin secondary current can be evaluated. I/ A H M P P P L L F H E F P P I F H RFig.2 - wavelet decomposition waveforms F F L P A 277 | P a g e
  3. 3. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 din M Fifo O P dout F rst (16 x 16) F Rd/w float r L notation P F Fig 5: Realization of 16 x 16 fifo logic forFig. 3. Digital architecture realized for Wavelet coefficient interfaceTransformation The obtained detail coefficients are down Each wavelet coefficient is decomposed by sampled by a factor of two to reduce the number ofa factor of 2 before passing it to the sample RAM. computation inturn resulting in faster operation. ToThe sample RAM is developed with 12 x 16 realize the decimator operation comparator logiclocation for holding the wavelet coefficient after with a feedback memory element is designed asevery high pass filter output. shown below. The filter logics are realized using MAC(7)(multiply and accumulate) operation where arecursive addition, shifting and multiplication clkoperation is performed to evaluate the outputcoefficients. The recursive operation logic is as Indexshown below. rs comparator t Index Filter (i) coeffi- cients Memory f(i) Down Filtered unit sampledInput coefficient coefficients Multiplier Addercoeffi- Fig 6: architecture for decimation by 2 logiccients 4. VHDL MODELING TO REALIZE DWTx(i) The proposed system is realized using Convolve VHDL language for it‟s functional definition. The d HDL modeling(8) is carried out in top-down Shifter approach with user defined package support for output floating point operation and structural modeling for y(i) recursive implementation of the filter bank logic. For the realization a package is defined with user defined record data type asFig 4 : Realization of recursive MAC operation type real_single is record Before passing the data to filter bank the sign : std_logic;fifo logic realized stores the data in asynchronousmode of operation, operating on the control signals exp: std_logic_vector(3 downto 0); mantissa:generated by the controller unit. On a read signal the std_logic_vector(10 downto 0);off-centered data is passed to the buffer logic. The end record;fifo logic is realized as shown below. The floating notation is implemented using 16 bit IEEE-754 standards as presented below. Sign. (1) Exp. (4) Mantissa (11) 278 | P a g e
  4. 4. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 secondary side transformer obtained after impulseThe floating-point addition, multiplication and test are discretized using matlab tool where eachshifting operation are implemented as procedures in coefficient is converted to 16-bit floating notationthe user defined package and are repeatedly called and passed to the test bench for HDL interface. Thein the implementation for recursive operation. The coefficients obtained from the filter bank afterprocedures(9) are defined as; convolution is then compared with the results obtained from the matlab decomposition forprocedure shifftl (arg1: std_logic_vector;arg2: accuracy evaluation.integer;arg3 :out std_logic_vector); library ieee;procedure shifftr (a:in std_logic_vector; b:in use work.math_pack1.all; useinteger;result: out std_logic_vector); ieee.std_logic_arith.all;procedure addfp (op1,op2: in real_single;op3: out use ieee.std_logic_unsigned.all; usereal_single) ; ieee.std_logic_1164.all; entity topmodule_wb isprocedure fpmult (op1,op2: in real_single;op3: out end topmodule_wb;real_single) ; architecture TB_ARCHITECTURE of topmodule_wb isfor performing the convolution operation, filtercoefficients are defined as constant in this package component topmodule port (and are called by name in filter implementation. clk : in std_logic; rst : in std_logic; start : inconstant std_logic; read1 : in std_logic);lpcof0: real_single:=(1,"0100","00001001000"); end component;constant signal STIM_clk : std_logic;lpcof1: real_single:=(0,"0100","11001010111");constant signal TMP_clk : std_logic; signal STIM_rst :lpcof2:real_single:=(0,"0110","10101100010"); std_logic; signal STIM_start : std_logic; signalconstant STIM_read1 : std_logic; signal WPL : WAVES_PORT_LIST; signal TAG :lpcof3:real_single:= 0,"0101","11101110100"); WAVES_TAG;constant hpcof0: signal ERR_STATUS: STD_LOGIC:=L;real_single:= (1,"0101","11101110100"); constanthpcof1:real_single:=(0,"0110","10101100010"); beginconstant CLOCK_GEN_FOR_clk: process beginhpcof2:real_single:=(1,"0100","11001010111");constant if END_SIM = FALSE then TMP_clk <= 0; waithpcof3:real_single:=(1,"0100","00001001000"); for 50 ns; elseusing the above definitions the filters are designed wait; end if;for high pass and low pass operation. The recursiveimplementation is defined as; if END_SIM = FALSE then TMP_clk <= 1; wait for 50 ns;for k in 1 downto 0 loop old(k):=shift(k); else wait; end if; end process;fpmult(old(k)(0),hpf(k+1),pro(k)(0)); ASSIGN_STIM_clk: STIM_clk <= TMP_clk;proper(j,k):=pro(k)(0); ASSIGN_STIM_rst: STIM_rstaddfp(acc(k)(0),pro(k)(0),acc(k)(0));acer(j,k):=acc(k)(0); <= WPL.SIGNALS(TEST_PINSpos(rst)+1); ASSIGN_STIM_start:shift(k+1):=shift(k); end loop; STIM_startfor the evaluation of the implemented design the test <= WPL.SIGNALS(TEST_PINSpos(start)+1);vectors are passed through the test bench generated UUT: topmodulefrom Matlab tool. The continuous output of port map( 279 | P a g e
  5. 5. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282=> ,clk => STIM_clk, rst => STIM_rst, start => coeff. equivalentSTIM_start, => „0‟,”1000”,”00011000110=> , 0.2245 ” 0.225 „1‟,”0011”,”01000011101read1 => STIM_read1, => ); -0.661 ” -0.66 „1‟,”0111”,”00010001000end TB_ARCHITECTURE; -0.002458 ” -0.00232end TESTBENCH_FOR_topmodule; „0‟,”0101”,”00011000001 0.124 ” 0.1245. RESULT „0‟,”0100”,”01000001000 The sampled input data and the comparison 0.0325 ” 0.0323of subsequent wavelet coefficients from MATLAB Approximate Coefficients :Program, HDL code is as shown below : Matlab DecimalInput Data : HDL output (Binary) coeff. equivalentOutput from 0.2254 „0‟,”0100”,”01000010001” 0.2243impulse test Digital binary dataas input -0.0884 „1‟,”1001”,”00000111000” -0.08740.21751 „0‟,”1010”,”11000000001” -0.02154 „1‟,”0101”,”01000100000” -0.021220.0158 „0‟,”0110”,”00001100001” 0.2245 „0‟,”0011”,”10000010001” 0.22350.0.365 „0‟,”0101”,”01100101000” 0.45457 „0‟,”0110”,”00010011100” 0.454350.0325 „0‟,”0100”,”01001110001”0.01245 „0‟,”0110”,”01001100000”Detail Coefficients at level 1 :Matlab Decimal HDL output (Binary)coeff. equivalent „0‟,”1001”,”001111001100.15192 ” 0.15171 „0‟,”0100”,”000101111010.003154 ” 0.00312 „0‟,”1001”,”011010101100.1245 ” 0.1243 „0‟,”0111”,”000101000100.22545 ” 0.2233 „0‟,”1000”,”000110100010.003214 ” 0.003113Detail Coefficients at level 2 : Fig. 7: Functional simulation result for designed DWT on Aldec’s simulator showing the detail andMatlab Decimal approximate coefficient obtained after filtration HDL output (Binary)coeff. equivalent0.211 „0‟,”1010”,”01010111000” 0.2110.00124 „0‟,”0011”,”00001001001” 0.001231.0024 „0‟,”0100”,”00010111000” 1.0024-0.036 „1‟,”0110”,”00101100000” -0.035-0.02145 „1‟,”0100”,”00011111001” -0.02142Detail Coefficients at level 3 :Matlab HDL output (Binary) Decimal 280 | P a g e
  6. 6. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 Fig 9: Routing of logical placement in targeted (xc2vpx70-7-ff1704) FPGAFig 8: functional simulation result for designedDWT on Aldec’s simulator showing input’s for thedesign The functional results obtained after theconvolution operation carried out for theimplemented filter design is shown in figure 7. Thecoefficients are generated from the discretized Fig 10. Logical utilization of CLB in targeted FPGAsamples passed from the test-bench interface wherethe stimulus are taken from the MATLAB The synthesis result for the designed DWT processor is presentedgenerated binary coefficients of the secondary sidepower transformer. The coefficients are compared Macro Statisticswith resolution coefficients obtained from the # Registers : 49MATLAB results and are almost found equal with # Multiplexers : 250.01 variations, resulting in high accuracy in # Tristates : 74computation. # Adders/Subtractors : 618 # Multipliers : 29 About 15 cycles of system clock for # Comparators : 128performing the operation. This time is Design Statistics # IOs : 26comparatively 85-90 % less as compared to the time Cell Usage : # BELS : 181taken for performing filtration operation in Minimum period : 5.220nsMATLAB simulation. The test vectors are passed (Maximum Frequency : 191.571MHz)through test bench for simulation as illustrated infigure 8. From the result it is observed that a logical count of 181 Basic element logic (BEL) are required6. FPGA REALIZATION for the realization of DWT processor. The real time The designed system is targeted onto xilinx Maximum operating frequency obtained is 191.571xc2vpx70-7-ff1704 FPGA device belonging to MHz. This operation frequency is considerablyvirtex2p family with a speed grade of –7. The higher than the current sample frequency and makeimplementation of deigned DWT processor is it more suitable for real time current analysis.illustrated in figure 9. The(10) logical routing can beobserved from the obtained Place and route result The power analyzer of xilinx tool is usedform the FPGA Editor option in xilinx synthesizer. for the evaluation of power consumption andIt is observed that about 40% area for the targeted thermal summary for the designed DWT processorFPGA is covered for the implementation of DWT for real time operation. from the report generatedprocessor. Figure 10 shows the logical utilization in the power consumed is about 204 mW undereach configurable logical blocks (CLB) in the operating condition with working temperature ofimplemented FPGA. The CLB‟s are connected in 25C, which are very suitable under real timecascade manner to obtain the functionality for the implementation.designed processor. Part : 2vp100ff1696-6 281 | P a g e
  7. 7. Meha Sharma, rewa Sharma / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 2, March -April 2013, pp.276-282 Data version : ADVANCED,v1.0,05-28-03 [1]. R. MLEWSKY, ”Five Years of Monitoring Power the Impulse Test of Power Transformer summary : I(mA) P(mW) with Digital Recorders and Transfer--------------------------------------------------------------- Function Method”, pp.1-6,CIGRE 1992---- .session 12-20. Total estimated power consumption [2]. W. Wang , Y.M.Li , Y.Qui “ Application : 204 of Wavelet Analysis to Detection of Vccint 1.50V : 100 150 Transformer Winding Deformation, Vccaux 2.50V : 20 50 10th ISH’ 97, pp 131-134 Montreal Vcco25 2.50V : 2 4 Qubec Canada 1997. Peter Hoffman AND Thermal summary: Surya Santoso, “ Power Quality--------------------------------------------------------------- Assessment via Wavelet Transform---- Analysis”, IEEE Transaction on PowerEstimated junction temperature : 25C Delivery Vol,.11,No 2 April 1996.Ambient temp : 25C [4]. Daubechies, I. (1990) “ The waveletCase temp : 25C transform, time/frequency location and signal analysis. IEEE Transactions onThe Register transfer logic (RTL) implementation Information Theory”, 36, 961-1005.for the designed processor is shown in figure 11. [5]. S.Masud "VLSI system for discrete wavelet transforms", PhD Thesis, Dept. of electrical engineering, The Queen‟s University of Belfast, 1999. [6]. Rioul, O. and M. Vetterli (1991) “ Wavelets and signal processing. IEEE Signal Processing Magazine”, 14-38. [7]. Vetterli, M. and J. Kovacevic (1995) “ Wavelets and Subband Coding”. Prentice Hall, Englewood Cliffs, NJ, U.S.A. [8]. HDL Designer Series User Manual, Software Version 2003.1,9 April 2003, Mentor Graphics Corporation 1996-2003. [9]. Modelsim 5.6 SE Performance Guidelines, Model Technology February 2002, User‟sFig 11. RTL implemented for the designed DWT Manual, Version 5.6e, Mentor Graphicsprocessor. Corporation 1996-2002. “XC4000E and XC4000X Series Field Programmable Gate7. CONCLUSION Arrays”, Xilinx 1999. FPGA implementation for DWT processorfor the analysis of power transformer faults isrealized. The implementation of DWT processor onFPGA results in high speed operation of automatedpower quality analyzer by replacing the existingfilter bank architecture (or) DSP based architectureresulting in more reliable operations for powerquality analysis. The implementation resultsobtained from xilinx synthesizer shows a very lowresource utilization with high speed real timeoperating frequency and low power consumption,with ambient temperature condition which are mostsuitable for real time installation in power qualityanalysis. The developed FPGA design could bemerged with advanced learning standards for thetotal automation of fast and reliable powertransformer protections in electrical power system.This facility leads to the concept ofreconfigurability, which is advantageous and nothigh resource consuming under remote applications.REFERENCES 282 | P a g e