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Vedic multiplier is based on ancient Indian Vedic mathematics that offers
simpler and hierarchical structure. Multivalued logic results in the effective utilization of
interconnections, which reduces the chip size and delay. This paper proposes a new design
of 4×4 Vedic multiplier using quaternary currentmode multivalued logic, equivalent to
iplier has
very low transistorcount and consumes very low power as compared to other multiplier
designs. Since the performance of a digital signal processor depends mainly on the
multipliers used, the proposed approach can greatly enhance the performance of a digital
signal processing system.
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