Realization of ternary logic based shift up, shift down using mosfet-2

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Realization of ternary logic based shift up, shift down using mosfet-2

  1. 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 240 REALIZATION OF TERNARY-LOGIC BASED SHIFT UP, SHIFT DOWN USING MOSFET Virang Jhaveri1 , Yash Jain2 , Vishesh Kamdar3 , Shanay Kothari4 1 (EXTC, D.J. Sanghvi College of Engineering, Mumbai, India) 2 (EXTC, D.J. Sanghvi College of Engineering, Mumbai, India) 3 (EXTC, D.J. Sanghvi College of Engineering, Mumbai, India) 4 (EXTC, D.J. Sanghvi College of Engineering, Mumbai, India) ABSTRACT In this paper, we discuss the practical realization of basic shift up and shift down ternary based logic gates. Current bit based circuitry limits the number of gate design. The present CMOS technology does not use depletion mode transistors. The prime objective in our work is to minimize the number of transistors used whilst retaining functionality, eliminate the use of resistors to lower the power consumption and reduce delay propagation. The reduction in the number of transistors is main focus as that enabled a more compact design. Keywords: Basic Gates, Integrated Circuit, MOSFET, Multi-Value Logic Design, Shift Up Down, Ternary Logic I. INTRODUCTION When we view ternary logic from a mathematically perspective it becomes apparent that there are twenty seven possible gate designs. Whereas when we consider a binary system for a dual bit input there is only the possibility of constructing four gates. Hence, it is apparent that the lack of hitherto unseen logic gates in the field of ternary logic has hampered further research in it. The use of new gates permits us to radically redesign familiar elements such as adders, subtractors, multiplexers, demultiplexers, encoders and decoders. Current ternary based design research is focused in the field of increasing the efficiency of previously designed ternary gates and ‘porting’ existing binary systems with ternary ones. Theoretically, the advantages offered are shorter decimal representation; ternary logic representation offers us a novel way of dealing with recurring decimals since it uses a base 3. Although we compromise accuracy for better computation the loss of data is minimal. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August, 2013, pp. 240-247 © IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET © I A E M E
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – II. TERNARY LOGIC Ternary logic functions are those functions where Kleene logic augments the conventional true and false of Boolean logic with a third value; unknown, indeterminate, irrelevant, or both. In this paper, the assignments of different numerical equivalents to these values are as follows: 0, 1, and 2 represent false, undefined, and true, respectively. Any n variable {X1,...,Xn} ternary function f (X) is de {0,1,2} n to {0, 1, 2}, where X {X1,...,Xn}. The basic operations of ternary logic can be de follows, where Xi, Xj= {0, 1, 2} [13]: Xi+ Xj= max{Xi, Xj} Xi• Xj= min{Xi, Xj} Xi`= 2− Xi where the operations +,•,` and are referred to as the OR, AND, and NOT in terna respectively. The fundamental gates in the design of digital systems are the inverter, the NOR gate, and the NAND gate. The assumed logic symbols are shown in Ta designed according to the convention de III. STEP DOWN GATE Step down gate is divided in two sections. (i) Limiting Circuit (ii) Inverter Circuit Limiting circuit for step down gate Fig International Journal of Electronics and Communication Engineering & Technology (IJECET), – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 241 Ternary logic functions are those functions where Kleene logic augments the conventional logic with a third value; unknown, indeterminate, irrelevant, or both. In this paper, the assignments of different numerical equivalents to these values are as follows: 0, 1, and 2 fined, and true, respectively. [1] ..,Xn} ternary function f (X) is defined as a logic function mapping {0,1,2} n to {0, 1, 2}, where X {X1,...,Xn}. The basic operations of ternary logic can be de where the operations +,•,` and are referred to as the OR, AND, and NOT in terna The fundamental gates in the design of digital systems are the inverter, the NOR gate, and the NAND gate. The assumed logic symbols are shown in Table I. The ternary gates are designed according to the convention defined by (1). Table (1) two sections. ircuit Fig. (1) – Simulated on LTSPICE Voltage Symbol -5 0 0 1 5 2 International Journal of Electronics and Communication Engineering & Technology (IJECET), August (2013), © IAEME Ternary logic functions are those functions where Kleene logic augments the conventional logic with a third value; unknown, indeterminate, irrelevant, or both. In this paper, the assignments of different numerical equivalents to these values are as follows: 0, 1, and 2 fined as a logic function mapping {0,1,2} n to {0, 1, 2}, where X {X1,...,Xn}. The basic operations of ternary logic can be defined as where the operations +,•,` and are referred to as the OR, AND, and NOT in ternary logic, The fundamental gates in the design of digital systems are the inverter, the NOR gate, ble I. The ternary gates are ircuit
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 242 Working – Limiting Circuit The limiting circuit is designed on the fact that the pmos conducts when the gate voltage is less than its Drain voltage and nmos conducts when the gate voltage is greater than its Drain voltage. When -5v is supplied via V2 The gate voltage of pmos(-5v) is less than its drain voltage (5v) and The gate voltage of nmos(-5v)is less than its drain voltage therefore pmos conducts and nmos doesn’t conduct .The output is 5v When 0v is supplied via V2 The gate voltage of pmos(0v) is less than its drain voltage (5v) and The gate voltage of nmos is same as its drain voltage therefore pmos conducts and nmos doesn’t conduct. The output is 5v When 5v is supplied via V2 The gate voltage of pmos(5v) is same as its drain voltage (5v) and The gate voltage of nmos(5v) is greater than its drain voltage(0v) therefore nmos conducts and pmos doesn’t conduct.The output is 0v The table(2) shows the truth table of the limiting circuit where the input and output are represented in their respective logic states. Table (2) Input Output 0 2 1 2 2 1 The Graph (1) shows the simulation of limiting circuit where the blue line is the output and the green line is the input. The input varies from -5V to 5V and the o/p varies from 5v to 0 V Graph(1)
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 243 The limiting circuit is the connected to a inverter circuit which is represented by Table (3)[2] Table (3) Input Output 0 2 1 1 2 0 Fig. (2) (Step Down Gate) Truth Table (Step Down Gate) IN Step Down(IN) 0 0 1 0 2 1 Working – Step Down The M2 and M4 complement the the trits provided by M1 and M3 present in the first stage.. When IN is 0V , M3 is activated therefore the output at mid stage is 5V and then it goes thru the NOT gate and the output is -5V which is the required output When IN is -5V , M3 is activated therefore the output at mid stage is 5V and then it goes thru the NOT gate and the output is -5V which is the required output When IN is 5V , M1 is activated therefore the output at mid stage is 0V and then it goes thru the NOT gate and the output is 0V which is the required output. The graph (2) shows the the simulation of the shift down gate.The red line is the zero reference line, the green line is the input line which starts at -5 V and the increases towards 5 V. The blue line is the output line.
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 244 Graph (2) IV. STEP UP GATE Step Up Gate is divided in two sections. (i). Limiting Circuit (ii). Inverter Circuit Limiting circuit for step up gate Fig. (3) – Simulated Using LTSPICE
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 245 Working – Limiting Circuit The limiting circuit makes is designed on the fact that the pmos conducts when the gate voltage is less than its Drain voltage and nmos conducts when the gate voltage is greater than its Drain voltage. When -5v is supplied via V2 The gate voltage of pmos(-5v) is less than its drain voltage (0v) and The gate voltage of nmos (-5v)is same as its drain voltage therefore pmos conducts and nmos doesn’t conduct.The output is 0v When 0v is supplied via V2 The gate voltage of pmos(0v) is same as its drain voltage (5v) and The gate voltage of nmos (0v) is greater than its drain voltage(-5v) therefore nmos conducts and pmos doesn’t conduct.The output is -5v . When 5v is supplied via V2 The gate voltage of pmos(5v) is greater than its drain voltage (0v) and The gate voltage of nmos(5v) is greater than its drain voltage(-5v) therefore nmos conducts and pmos doesn’t conduct.The output is -5v The table(4) shows the truth table of the limiting circuit where the input and output are represented in their respective logic states. Table (4) Input Output 0 1 1 0 2 0 The graph (3) shows the simulation of limiting circuit where the blue line is the output and the green line is the input.the i/p varies from -5v to 5v and the o/p varies from 0 V to -5 V. Graph (3)
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 246 The limiting circuit is the connected to a inverter circuit which is represented by table (5)[2] Table (5) Input Output 0 2 1 1 2 0 Fig. (4) (Step Up Gate) Truth Table (step up gate) IN Step Up (IN) 0 1 1 2 2 2 Working – Step Up Gate The M2 and M4 complement the the trits provided by M1 and M3 present in the first stage.. When IN is -5 V , M3 is activated therefore the output at mid stage is 0V and then it goes thru the NOT gate and the output is 0V which is the required output When IN is 0 V , M1 is activated therefore the output at mid stage is -5V and then it goes thru the NOT gate and the output is 5V which is the required output When IN is 5 V , M1 is activated therefore the output at mid stage is -5V and then it goes thru the NOT gate and the output is 5V which is the required output The graph (4) shows the simulation of the shift down gate. The red line is the zero reference line, The green line is the input line which starts at -5 V and the increases towards 5 V. The blue line is the output line.
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME 247 Graph (4) V. IMPLEMENTATIONS The above circuits have been implemented and simulated in LT Spice. VI. APPLICATION S The immediate forseeable applications of the shift up and shift down ternary gates are their use to develop new designs for traditional combinational circuits like adders and subtractors. The shift up and shift down gate design can be used to realize other still unknown gate designs. VII. FUTURE SCOPE Since the data usage by simple as well as complex circuitry goes on increasing, we are reaching a point where the limitations of Moores law become self apparent. Hence there is an immediate real world need to replace our ‘bit’ based systems with the ‘trit’ based system. The use of these gates is to build the combinational circuits required to build a ternary ALU. VIII. REFERENCES 1. Standard Ternary Logic by by Douglas W. Jones THE UNIVERSITY OF IOWA Department of Computer Science http://homepage.cs.uiowa.edu/~jones/ternary/logic.shtml. 2. Implementation of Ternary Based Logic Gates. Virang Jhaveri, Shanay Kothari, Yash Jain ISBN No. 9789382880233. 3. Amit Nigam, “Enrichment Towards the Design of Efficient 4 Bit Reversible Subtractor using TR Gate: A Low Power Application”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 4, 2013, pp. 1 - 12, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.

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