International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 097...
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Implementation and validation of multiplier less fpga based digital filter

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Implementation and validation of multiplier less fpga based digital filter

  1. 1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME348IMPLEMENTATION AND VALIDATION OF MULTIPLIER LESSFPGA BASED DIGITAL FILTERJaya Koshta1,Vineeta Saxena(Nigam)2,Rakesh .K Arya31(Electronics & Communication Department,BIRTS,Bhopal,India)2(Electronics & Communication Department,UIT-RGPV,Bhopal,India)3(Senior resource scientist, MPCST,Bhopal,India)ABSTRACTFinite impulse-response filters (FIR filters) are commonly used in digital signalprocessing applications and traditionally implemented using ASICs or DSP-processors.Nowadays, Field Programmable Gate Array (FPGA) technology is widely used in digitalsignal processing area because FPGA-based solution can achieve high speed due to itsparallel structure and configurable logic, which provides great flexibility and high reliabilityin the course of design and later maintenance. However, the limitation of resources on anFPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, requirecompact implementations of the circuits. Hence, FIR filter is implemented using distributedarithmetic technique which uses look-up table with offset binary coding. This paper describesan approach for implementation of FIR filter using distributed arithmetic, based on fieldprogrammable gate arrays (FPGAs).The experimental results shows that implementation oflow pass FIR filter using DA technique with offset binary coding requires less resourceutilization inside FPGA as compared to implementation of FIR filter using conventionalmultiply and accumulate (MAC) technique. The advantages of the FPGA approach to FIRfilter implementation include higher sampling rates than are available from traditional DSPchips, lower costs than an ASIC for moderate volume applications and more flexibility thanthe alternate approaches.Keywords – Binary offset coding, distributed arithmetic, FIR filter, FPGA , Look-up tableINTERNATIONAL JOURNAL OF ELECTRONICS ANDCOMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)ISSN 0976 – 6464(Print)ISSN 0976 – 6472(Online)Volume 4, Issue 2, March – April, 2013, pp. 348-356© IAEME: www.iaeme.com/ijecet.aspJournal Impact Factor (2013): 5.8896 (Calculated by GISI)www.jifactor.comIJECET© I A E M E
  2. 2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME3491. INTRODUCTIONIn general, Digital filters are divided into two categories, including Finite ImpulseResponse (FIR) and Infinite Impulse Response (IIR). And FIR filters are widely appliedto a variety of digital signal processing areas for the virtues of providing linear phase andsystem stability. Compared to IIR filters, FIR filters have simple and regular structureswhich are easy to implement on hardware. However FIR filters require higher number oftaps compared to IIR filters to achieve the same frequency specification. FIR filterimplementation on FPGA requires special attention as area, power, speed constraints haveto be satisfied. A number of filter architectures for FPGA implementation exist. Out ofthese, Distributed Arithmetic (DA) architecture yields better area, power and speed tradeoff balance.A discrete-time linear finite impulse response (FIR) filter generates the output y[n]as a sum of delayed and scaled input samples x[n] via the equation10Nk kky w x−== ∑ (1)A typical digital implementation will require N multiply-and-accumulate (MAC)operations, which are expensive to compute in hardware due to logic complexity,area usage, and throughput. Alternatively, the MAC operations may be replaced bya series of look-up-table (LUT) accesses and summations. Such an implementationof the filter, known as distributed arithmetic (DA), achieves higher throughput andlower logic complexity at the cost of increased memory usage. Recent advances inmemory design technology have resulted in shrinking memory sizes, making this tradeoffan attractive option. Distributed Arithmetic (DA) appeared as a very efficient solutionespecially suited for LUT-based FPGA architectures. This technique, first proposed byCroisier et al[1], is a multiplier-less architecture that is based on an efficient partitionof the function in partial terms using 2’s complement binary representation of data. Thepartial terms can be pre-computed and stored in LUTs. The flexibility of this algorithm onFPGAs permits everything from bit-serial implementations to pipelined or full-parallelversions of the scheme, which can greatly improve the design performance. The mainproblem with DA is that the requirement of memory/LUT capacity increasesexponentially with the order of the filter, given that DA implementations need 2K-words(K being the number of taps of the filter). That constitutes a first obstacle for FIR filters ofhigh order.In this paper FIR filter is implemented using distributed arithmetic with offsetbinary coding so that the memory size is reduced by a factor of 2 to 2K-1.Also the resourceutilization inside FPGA of FIR filter implemented using DA technique with offset binarycoding is compared with FIR filter implemented using conventional MAC technique.2. DISTRIBUTED ARITHMETICDistributed arithmetic (DA) is a bit-serial operation that computes the innerproduct of two vectors (one of which is a constant) in parallel. DA eliminates the need formultiply operations by using lookup tables (LUTs).The right balance among versions is
  3. 3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME350tied to specifications for a given application, and basically depends on requirements interms of hardware cost and throughput. In each case, the designer has to trade bandwidthfor area.Conventional Distributed arithmeticConsider a discrete N-order FIR filter with constant coefficients, and input samplescoded as B-bit two’s complement numbers with only the sign bit to the left of the binarypoint as:101( ) 2Bjk kjjx n k x x−−=− =− +∑ (2)Using (1) to compute the FIR output gives100 1 0( ) + [ ]2N B Njk k k kjk j ky n w x w x−−= = == −∑ ∑ ∑ (3)With0Nj k kjkC w x== ∑ where j= 1to B-1 and 0 00Nk kkC w x== −∑ , equation (3) can be rewrittenas10( ) 2Bjjjy n C−−== ∑ (4)Since the term Cj depends on xk,j values and has only 2Npossible values, it ispossible to precompute them and store them in look-up table or in read onlymemory[2],[3]. An input set of N bits (x0j,x1j… xN-1,j) is used as an address to retrieve thecorresponding Cj values. These intermediate results are accumulated in B clock cycles toproduce one y value. This leads to multiplier free realization of FIR filter.Table I shows the contents of the look-up table for N = 4. Fig.1 shows a typicalarchitecture for FIR filter using conventional distributed arithmetic. The shift-accumulator is a bit-parallel carry-propagate adder that adds the LUT content to theprevious accumulated result. The inverter and the MUX are used for inverting the outputof the LUT in order to compute CB-1 and the control signal S is 1 when j = B-1 and 0otherwise. The computation runs from j = 0 to j =B-1 and the result is available in bitparallel format after B clock cycles. This approach corresponds to bit serial arithmetic.However the main problem with DA is that the requirement of memory/LUT capacityincreases exponentially with the order of the filter, given that DA implementations need2K– words (K being the number of taps of the filter). That constitutes a first obstacle forFIR filters of high order. Therefore offset binary-coding is introduced that can reduce theLUT size by a factor of 2 to 2N-1.
  4. 4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME351Table IContent of LUT (N =4)x0,j x1,j x 2,j x 3,j Content of LUT0 0 0 0 00 0 0 1 w30 0 1 0 w20 0 1 1 w2 + w30 1 0 0 w10 1 0 1 w1 + w30 1 1 0 w1 + w20 1 1 1 w1 + w2 +w31 0 0 0 w01 0 0 1 w0 + w21 0 1 0 w0 +w21 0 1 1 w0 +w2 + w31 1 0 0 w0 + w11 1 0 1 w0 +w1 + w31 1 1 0 w0 + w1 +w21 1 1 1 w0 + w1 + w2 + w3Fig. 1 Implementation of conventional distributed arithmetic FIR filter3. SUGGESTED METHODOLOGY FOR FIR FILTER IMPLEMENTATIONIn suggested methodology for FIR filter implementation offset binary coding is usedfor distributed arithmetic. The offset-binary coding (OBC) is used to reduce the look-up tablesize by a factor of 2 to 2N-1.Also to increase the speed of FIR filter look-up table partitioningcan also be done.Equation (2) can be written as:1( ) { ( ) [ ( )]}2x n k x n k x n k− = − − − (5)
  5. 5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME3521( 1)01( ) 2 2Bj Bk kjjx n k x x−− − −=− − = − + +∑ (6)Substituting (2) and (6) into (5),1( 1)0 011( ) [ ( ) ( )2 2 ]2Bj Bk k kj kjjx n k x x x x−− − −=− = − − + − −∑ (7)By defining kjD as kj kjx x− , the output from FIR filter can be written as1( 1)00 1( ) [ 2 2 ]2N Bj Bkk kjk jwy n D D−− − −= == − + −∑ ∑1( 1)00 1 0 0[ ]2 22 2 2N B N Nk kj j Bk k kk j k kw Dw D w−− − −= = = == − + −∑ ∑ ∑ ∑ (8)Defining jE as0 2Nk kjkw D=∑ ,and extraE as0 2Nkkw=∑ equation (8) can be rewritten as1( 1)01( ) 2 2Bj Bj extrajy n E E E−− − −== − + −∑ (9)Equations (5)-(9) characterize the OBC scheme. Table II shows the content of the look-up table.Table IIContent of LUT with OBC coding(N=4)x0,j x1,j x 2,j x 3,j Content of LUT0 0 0 0 -(w0 + w1 + w2 + w3) / 20 0 0 1 -(w0 + w1 + w2 - w3) / 20 0 1 0 -(w0 + w1 - w2 + w3) / 20 0 1 1 -(w0 + w1 - w2 - w3) / 20 1 0 0 -(w0 - w1 + w2 + w3) / 20 1 0 1 -(w0 - w1 + w2 - w3) / 20 1 1 0 -(w0 - w1 – w2 + w3) / 20 1 1 1 -(w0 - w1 - w2 - w3) / 21 0 0 0 (w0 - w1 – w2 - w3) / 21 0 0 1 (w0 - w1 -w2 + w3) / 21 0 1 0 (w0 - w1 + w2 - w3) / 21 0 1 1 (w0 - w1 + w2 + w3) / 21 1 0 0 (w0 + w1 - w2 - w3) / 21 1 0 1 (w0 + w1 - w2 + w3) / 21 1 1 0 (w0 + w1 + w2 - w3) / 21 1 1 1 (w0 + w1 + w2 + w3) / 2
  6. 6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME353It is obvious that the Ej values are mirrored along the line between the 8-th and the 9-th rows in the LUT table. In other words the term Ej has only 2 N-1possible values dependingon xk,j values. Therefore it is possible to reduce the LUT size by a factor of 2[4-5]. Table IIIillustrates the content of LUT. Fig. 2 shows implementation of FIR filter using OBC coding.The computation starts from the lsb of xi ,i.e., j=0.The XOR gates are used for addressdeciding, the MUX with the constant Eextra provides the initial value to the shift –accumulatorand the MUX after the LUT is used to inverse the output of LUT when j= B-1.Two controlsignals S1 and S2 are required, where S1 is 1 when j = B-1 and 0 otherwise, and S2 is 1 whenj=0 and 0 otherwise.Table III Content of reduced LUT for N=4x1,j x2,j x 3,j Content of LUT0 0 0 -(w0 + w1 + w2 + w3) / 20 0 1 -(w0 + w1 + w2 - w3) / 20 1 0 -(w0 + w1 - w2 + w3) / 20 1 1 -(w0 + w1 - w2 - w3) / 21 0 0 -(w0 - w1 + w2 + w3) / 21 0 1 -(w0 - w1 + w2 - w3) / 21 1 0 -(w0 - w1 - w2 + w3) / 21 1 1 -(w0 - w1 - w2 - w3) / 2Fig. 2 Implementation of distributed arithmetic FIR filter using OBC codingThe look-up table (LUT) of distributed arithmetic increases exponentially with N.Generally, LUT access time can be a bottleneck for the speed of filter, especially when LUTsize is large. Therefore, reducing the LUT size is very important[6]. So to reduce the LUTsize one possible solution is to divide the N address bits of the LUT into N/K groups of Kbits. Hence it is possible to decompose the LUT of size 2N-1into N/K LUTs of size 2Kandadd the outputs of these LUTs using multi-input accumulator.
  7. 7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME3544. RESULTSThe proposed methodology is implemented for 8-tap low pass FIR filter. The FIRfilter is simulated and synthesized using Xilinx ISE on Spartan board. The coefficients offilter are truncated to four decimals places, scaled to signed integer and are represented in 2’scomplement form. The precision for inputs and coefficients used are 8 and 12 bitsrespectively. The results of offset binary coding Distributed arithmetic FIR filter is comparedwith conventional multiply and accumulate technique of FIR filter implementation. Fig. 3shows the simulation results for FIR filter implemented using MAC technique. Fig. 4 showsthe simulation results for FIR filter implemented using DA using offset binary codingtechnique.Fig.3 Simulation result for FIR filter implemented MAC technique.Fig.4 Simulation result for FIR filter implemented using DA using offset binary codingtechnique.
  8. 8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME355Table IV compares the resource utilization of FIR filter on FPGA implemented using bothMAC technique and DA with offset binary coding technique.Table IVDevice utilization summary for FIR filter designed using MAC and DA with offset binarycodingSelected Device: Spartan 2- xc2s200-5pq208MAC DANumber of SliceFlip Flops:101 out of470468 out of 4704Number of 4 inputLUTs:319 out of2352250 out of 2352Number ofoccupied Slices:291 out of4704205 out of 4704Number ofGCLKs:1 out of 4 1 out of 4Total equivalentgate count fordesign 5423 2423From Table IV it is seen that DA based implementation of FIR filter requires lessresources inside FPGA as compared to MAC based implementation of FIR filter. Also it isseen that DA-based filters exhibit lower gate counts than their MAC counterparts becausethey dont require multipliers.5. CONCLUSIONDistributed Arithmetic has proved to be an area efficient technique of FIR filterimplementation. While using it, special care is required against exponential growth of LUTsize. Slicing of LUT of desired length, gives an effective solution, particularly, for high orderfilter designs. The FIR filters implemented in FPGAs provide the designer tremendousflexibility in terms of the number of filter taps and changes in existing coefficients.
  9. 9. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME356REFERENCES[1] Croisier, D. J. Esteban, M. E. Levilion, and V. Rizo, Digital Filter for PCM EncodedSignals, U.S. Patent No. 3,777,130, issued April, 1973.[2] C.S Burrus,Digital filter structures described by distributed arithmetic, IEEE Trans. OnCircuits and Systems, Dec. 1977.[3] A. Peled and B. Liu, A new hardware realization of digital filters, IEEE Trans.Acoustics, Speech and Signal Processing, vol. ASSP- 22, no. 6, pp. 456-462, Dec1974.[4] J. Choi, S. Shin and J. Chung, Efficient ROM size reduction for distributed arithmetic,in Proceedings of the IEEE ISCAS, Geneva, Switzerland, May 2000, vol. 2, pp. 61-64.[5] H. Yoo and D. V. Anderson, Hardware-Efficient Distributed Arithmetic ArchitectureFor High-OrderDigital Filters, IEEE International Conference on Acoustics Speech and SignalProcessing,CASSP,pp.125-128, 2005.[6] Shanthala S, and S. Y. Kulkarni, High Speed and Low power FPGA Implementation ofFIR Filter for DSP Applications, European Journal of Scientific Research, 2009[7] Martinez-Peiro, J. Valls, T. Sansaloni, A.P. Pascual, and E.I. Boemo, A Comparisonbetween Lattice, Cascade and Direct Form FIR Filter Structures by using a FPGA Bit-Serial DA Implementation, in Proc. IEEE International Conference on Electronics,Circuits and Systems, 1999, Vol. 1,pp. 241 – 244.[8] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation.New York: Wiley, 1999.[9] S. A. White, Applications of distributed arithmetic to digital signal processing: Atutorial review, IEEE Acoust. Speech Signal Processing Mag., vol 6,pp.4-19 , July1989.[10] M. A. Majed and Prof. C.S. Khandelwal, “Efficient Dynamic System Implementationof FPGA Based Pid Control Algorithm for Temperature Control System”, InternationalJournal of Electrical Engineering & Technology (IJEET), Volume 3, Issue 2, 2012,pp. 306 - 312, ISSN Print : 0976-6545, ISSN Online: 0976-6553.[11] G.Prasad and N.Vasantha, “Design and Implementation of Multi Channel FrameSynchronization in FPGA”, International journal of Electronics and CommunicationEngineering &Technology (IJECET), Volume 4, Issue 1, 2013, pp. 189 - 199, ISSNPrint: 0976- 6464, ISSN Online: 0976 –6472.[12] Sriadibhatla Sridevi, Dr. Ravindra Dhuli and Prof. P. L. H. Varaprasad, “FPGAImplementation of Low Complexity Linear Periodically Time Varying Filter”,International journal of Electronics and Communication Engineering & Technology(IJECET), Volume 3, Issue 1, 2012, pp. 130 - 138, ISSN Print: 0976- 6464,ISSN Online: 0976 –6472.

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