20120140505014

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20120140505014

  1. 1. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 117 MODELING AND CONTROL OF A FRONT END CONVERTER WITH LEAST DISTORTION AND IMPROVED POWER FACTOR Renjith Kumar D Assistant Professor, Department of Electrical and Electronics Engineering College of Engineering Adoor, Kerala, India ABSTRACT This paper proposes Front End Conversion (FEC) using Pulse Width Modulated Voltage Source Converter (PWMVSC) with a suitable input filter as a viable solution to improve the input spectral quality which confines the harmonic parameters within acceptable standards and regulations. The input current is nearly sinusoidal with least harmonic distortion and input power factor is adjustable though normally kept at unity. The active converter provides consistently stable dc voltage and has regeneration capability. Better attenuation to switching frequency ripple is obtained with higher value of input line reactor but it increases the size, cost and losses. In this study, the synchronous reference frame control strategy is adopted and conventional proportional-integral (PI) controllers are used for controlling currents and dc bus voltage. The synchronous reference frame strategy eliminates cross coupling between the d and q phases and allows separate control of real and reactive power. Successful simulation is also carried out with designed values. Keywords: Front End Conversion (FEC), PI Controllers, Point of Common Coupling (PCC), Pulse Width Modulated Voltage Source Converter (PWMVSC), Sinusoidal Pulse Width Modulation (SPWM). 1. INTRODUCTION The exponential growth of conventional power electronic non linear loads such as inverters, uninterruptible power supplies, adjustable speed drives, induction furnaces etc. are ever worsening the performance of common electrical grids and other loads connected, through harmonic pollution. Most of the power electronic loads employ conventional diodes and thyristor rectifiers for front end conversion stage. They draw highly distorted current at poor input power factor, consequently INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET) ISSN 0976 - 6480 (Print) ISSN 0976 - 6499 (Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME: www.iaeme.com/ijaret.asp Journal Impact Factor (2014): 7.8273 (Calculated by GISI) www.jifactor.com IJARET © I A E M E
  2. 2. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 118 distorting the grid voltage and spreading the harmonic pollution widely which causes either mal operation or damage to the other sensitive loads connected at the common grid [1]. The disadvantages of traditional filtering mechanisms led to the acceptance of active power filters, PWM based active rectifiers etc. The development of high power semiconductor switches with high switching frequency along with multilevel inversion capability and advanced control strategies has improvised font end conversion stages so that the harmonic pollution can be confined to acceptable levels and standards. These converters improves the overall input power factor and draws sinusoidal input currents. For PWM Voltage Source Rectifiers benefits like power regeneration, low harmonic distortion, unity power factor, reactive power compensation and controlled dc link voltage can be obtained [2]. The operation principle is based on direct sinusoidal current generation free from harmonics using high frequency operating solid state switches instead of trying to filter out the harmonics after they have been created. The paper presents the modeling and control of front end converters with decoupled and linear d-q axes dynamics. The control loops can be treated as first order systems with improved tracking capability. The overall performance can be improved by increasing the order of filtering at the input side of the active rectifiers. 2. PWMVSR TOPOLOGY Fig. 1: Basic configuration of PWMVSR interfacing grid and load Fig. 1 shows the basic configuration of the PWMVSR interfacing the grid and load. The load can be either direct dc load or an inverter feeding ac load [3]. The Insulated Gate Bipolar Transistor (IGBT) module along with input and output filters draws undistorted sinusoidal current from the mains thus maintaining the power quality at the Point of Common Coupling (PCC) as per standards. The input line reactors are more efficient and economic comparatively even though the high frequency current harmonics due to high frequency switching of the converter increases the losses and stresses in them. The DC link voltage is maintained stable due to high capacitance on DC side resulting in high drive dynamic performance. The high frequency PWM strategy improves the input current waveform by pushing the dominant harmonics to higher frequencies which can be easily filtered [1]. The instantaneous difference between the input power and output power is the reason for charging or discharging of dc link capacitor. 3. CONTROL STRATEGY The modulation parameters of the power converter are controlled in order to control the input current to be at unity power factor. The controller is designed in synchronously rotating reference frame so that all the quantities to be controlled are transformed into dc quantities. So a simple proportional integral (PI) controller can be used to attain zero steady state error and high dynamic response [4].
  3. 3. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 119 The dc link voltage loop is the outer loop and the current loops are the inner loops [5]. Both the inner current loops are assigned with identical PI controllers. The internal loops which are comparatively faster are designed to achieve short settling times and fast harmonic tracking whereas the outer loop for optimum regulation and stability. The dc link voltage loop balances the active power flow through regulating the dc bus capacitor voltage. DC link voltage is therefore controlled by adjusting the amplitude of the input ac currents. This is accomplished with a dc capacitor and the feedback control loop shown in Fig. 2 through which the dc link voltage is kept at a desired reference value [2]. Fig. 2: Feedback control loop to maintain dc voltage For the current control loops, as d-q reference frame rotating synchronously with the fundamental supply voltage frequency is used, conversions from three phases to d-q reference frames are needed [2]. These transformations have to be performed on both voltages and currents. The corresponding unit vectors for transformation are derived from the supply voltages. The overall block diagram is shown in Fig. 3. Fig. 3: Block diagram of the vector control of the sinusoidal FEC
  4. 4. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 120 With the help of line current sensors, the line currents are measured and transformed to the d- q reference frame using generated unit vectors. The output of the dc voltage PI controller added to the transformed load current component gives the d component of the line current reference (idref). The q component of line current reference (iqref) is generally set to zero to make input power factor unity. It can be allotted some value in applications requiring compensation requirements or active filtering. Here ωL terms are included to eliminate the coupling effect among the d and q components which help to reduce the current control loops to first order plants and improve their tracking capability. Decoupled and linear dynamics are thus obtained. The line current PI controllers gives d and q components of the voltage across the line inductance to which the cross coupling terms are included as per control equations. Subtracting these voltages from the supply voltage d and q components gives the converter voltages from the ac sides which after suitable inverse transformations are used to get the modulation signals for proper switching of the devices. Harmonics causes due to high frequency switching, sudden changes in load, dc ripples etc. A PWM scheme would ensure that the inverter voltage is free from low order harmonic distortion which results in input filter minimization. Here, Sinusoidal PWM (SPWM) is adopted. By changing the amplitude of the fundamental and its phase shift with respect to the mains voltage, the converter can be operated in all the four quadrants. After transforming the three phase quantities to d-q reference frame quantities, the set of system equations in the d-q frame may be written as ‫ۺ‬‫ܛ‬ ‫۷܌‬‫܌‬ ‫ܜ܌‬ ൌ െ‫܀‬‫ܛ‬۷‫܌‬ ൅ ‫܄‬‫܌‬ െ ‫܄‬ܑ‫܌‬ ൅ ૑‫ۺ‬‫ܛ‬۷‫ܙ‬ (1) ‫ۺ‬‫ܛ‬ ‫۷܌‬‫ܙ‬ ‫ܜ܌‬ ൌ െ‫܀‬‫ܛ‬۷‫ܙ‬ ൅ ‫܄‬‫ܙ‬ െ ‫܄‬ܑ‫ܙ‬ െ ૑‫ۺ‬‫ܛ‬۷‫܌‬ (2) where Id and Iq are the d axis and q axis line current components, Vd and Vq are the d axis and q axis supply voltage components,Vid and Viq are the d axis and q axis converter voltage components and Ls and Rs are the input filter inductance and resistance respectively. Two quantities ‫܃‬‫܌‬ ൌ ‫܄‬‫܌‬ െ ‫܄‬ܑ‫܌‬ ൅ ૑‫ۺ‬‫ܛ‬۷‫ܙ‬ (3) ‫܃‬‫ܙ‬ ൌ ‫܄‬‫ܙ‬ െ ‫܄‬ܑ‫ܙ‬ െ ૑‫ۺ‬‫ܛ‬۷‫܌‬ (4) are defined. Simple PI controllers as shown in Fig. 4 are sufficient to obtain a satisfactory response of the d axis and q axis control. Making the current control loop transfer function as a first order system for simplicity, the proportional gain of the controller, ۹‫ܘ‬ ൌ ‫ۺ‬‫ܛ‬ ‫܂‬ܑ (5) and the integral gain of the controller, ۹ܑ ൌ ‫܀‬‫ܛ‬ ‫܂‬ܑ (6) where Ti is the time constant of the current control loop for the desired speed of response.
  5. 5. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 121 Fig. 4: PI Current Controllers The power for the switching losses and ohmic losses in the circuit is drawn from the dc bus capacitor along with the dc load current. The reduction in dc bus voltage is compensated by drawing appropriate amount of active power from the grid. The dc bus voltage controller is modeled as shown in Fig. 5. As the capacitor with capacitance C has a finite bulk resistance (Rb), a simple PI controller is designed to control the dc bus voltage. Fig. 5: DC bus voltage controller Here also making the voltage control loop transfer function a first order system, the proportional gain of the controller, ۹‫ܘ‬ ൌ ۱ ‫܂‬‫ܞ‬ (7) and the integral gain of the controller, ۹ܑ ൌ ૚ ‫܀‬‫܊‬‫܂‬‫ܞ‬ (8) where Tv is the time constant of the voltage control loop to get desired speed of response. Load feed forward control is used to provide faster response to load changes that can be obtained by monitoring the dc bus voltage alone. The current through the capacitor, load current (Io) and dc current (Idc) are related by the equation ۱ ‫܄܌‬‫܋܌‬ ‫ܜ܌‬ ൌ ۷‫܋܌‬ െ ۷‫ܗ‬ (9) 4. DESIGN OF FILTER ELEMENTS The value of the input filter inductance is related with the switching frequency in order to achieve a limited harmonic distortion at the input current or to confine the current ripple generated mainly due to the PWM switching of the VSC. The selection of the ripple current is a trade off
  6. 6. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 122 among inductor size, IGBT switching and conduction losses, inductor losses etc. Typically, the ac side ripple current can be chosen as 10%-25% of rated current. The equation for inductance value in the converter side can be deduced as ‫ۺ‬‫ܛ‬ ൌ ۲‫܄‬‫܋܌‬ሺ૚ି۲ሻ ૛√૛ ∆۷܎‫ܟܛ‬ (10) where D is the duty cycle ∆I is the permitted rms current ripple and fsw is the switching frequency Vdc is the DC bus voltage The permitted ripple component on the dc bus voltage decides the value of the required capacitor. The dc bus capacitance is given by ۱ ൌ ‫۾‬ܑ‫ܖ‬ઢ‫ܜ‬ ‫܄‬‫܋܌‬ઢ‫܄‬ (11) where Pin is the input power at rated condition, ∆t is the discharge period (to load) and ∆V is the ripple voltage allowed at the dc bus 5. SIMULATION RESULTS The system parameters taken for the calculation of the filter components of the FEC with L configuration, for a load rating of 7 kW, are given as follows; Rated active power of the system, P : 7 kW RMS value of grid line voltage, Vg : 415 V Frequency of grid voltage, f : 50 Hz Switching frequency of PWM converter, fsw : 10 KHz DC voltage of converter, Vdc : 700 V Current controller time constant, Ti : 150 µs Voltage controller time constant, Tv : 20 ms Assuming input power factor close to unity and an efficiency of 95% for the front end rectifier, rated input grid current, I୥ ൌ ୔ √ଷ୚ౝ୶଴.ଽହ ൌ 10.25 A For 2% dc voltage ripple and a discharge period of 1 ms, from Eqn. (11), dc bus capacitance, C ൌ 700 µF The current ripple will be largest for a duty cycle of 50%. From Eqn. (10), inductance on the converter side allowing 10% rms current ripple, Lୱ ؆ 6 mH The simulation results using PSIM for the front end converter with L filter at full load and Iqref = 0 A are given in Fig. 6. It is obvious that the input power factor is nearly unity with less harmonic distortion. Fig. 7 and Fig. 8 shows the FFT (Fast Fourier Transform) of the line current. The harmonics are pushed to high frequencies and can be filtered easily. Fig. 9 shows the stabilty and regulation owing to sudden changes in load. The power reversal capability is demonstrated in Fig.10. Designed values of filter elements and controller time constants are taken for the simulation analysis.
  7. 7. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 123 Fig. 6: ‘a’ phase voltage and current (current scaled by 10) Fig. 7: FFT of line current Fig. 8: FFT of line current enlarged at switching frequency Fig. 9: DC voltage and grid currents when full load is suddenly applied
  8. 8. International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 5, May (2014), pp. 117-124 © IAEME 124 Fig. 10: Power reversal capability (current scaled by 10) 6. CONCLUSION Due to the ever increasing number of nonlinear loads, revised regulations and standards impose more stringent limits to the harmonic pollution injected by different power electronic converters. Sinusoidal front end converters have been discussed as a viable solution for mitigating the harmonics in an effective way. Modeling of PWMVSR as front end converter has been discussed in detail. Design of controllers in synchronously rotating reference frame and the control strategy were discussed. Simulation of the model with inductance filter at the input has been done and the results proved the capability of the device to operate at nearly unity power factor with low input current distortion, high dynamic performance, power regeneration capability etc. 7. ACKNOWLEDGEMENT The author would like to thank CDAC Trivandrum and Faculty Members of Department of Electrical and Electronics Engineering, NIT Calicut for the immense help and the facilities extended for completing the task. REFERENCES [1] I. C. Evans and A. H. Hoevenaars, “ Meeting harmonic limits on marine vessels”, Electric Ship Technologies Symposium, ESTS’07, IEEE, May 2007, pp. 115-121. [2] J. Rodriguez et al. “PWM regenerative rectifiers: state of the art”, IEEE Transactions on Industrial Electronics, vol.52, no.1, Feb 2005, pp. 5-22. [3] T. Narasa Reddy et al. “Modeling and simulation of PWM line converter feeding to vector controlled induction motor drive and 3 level SVM based PMSM drive”, International Journal of Recent Trends in Engineering, vol.2, no.5, Nov 2009, pp.268-272 [4] C. Wessels et al. “Active damping of LCL filter resonance based on virtual resistor for PWM rectifiers - Stability analysis with different filter parameters”, Power Electronics Specialists Conference, PESC 2008, IEEE, 15-19 June 2008, pp.3532 – 3538. [5] M. H. Bierhoff and F. W. Fuchs, “Active damping for 3 phase PWM rectifier with high order line side filters”, IEEE Transactions on Industrial Electronics, vol. 56, no. 2, Feb 2009, pp. 371-379. [6] Mahavir Singh Naruka, D S Chauhan and S N Singh, “Power Factor Improvement in Switched Reluctance Motor Drive using PWM Converter”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 4, 2013, pp. 48 - 55, ISSN Print: 0976-6545, ISSN Online: 0976-6553.

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