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Implementation of a fhss transceiver on an sdr


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Implementation of a fhss transceiver on an sdr

  1. 1. Implementation of a FHSS transceiver on an SDR platform<br />If I have seen further it is only by standing on the shoulders of giants<br />
  2. 2. SDR platform<br />RF module<br />Data conv module<br />DSP module<br />
  3. 3. Specs of an SDR platform<br />DSP Module:<br /><ul><li>DSP CPU clock 594 MHz
  4. 4. ARM CPU clock 297 MHz
  5. 5. NAND flash memory 128 MB
  6. 6. DDR2 SDRAM 128 MB
  7. 7. FPGA Virtex IV</li></li></ul><li>Specs of an SDR platform<br />Data Conv Module:<br />DC specs:<br />Input channels 2<br />Input channels resolution 14 bit<br />Out put channels 2<br />Output channel resolution 16 bit<br />AC specs:<br />Acquisition Sample Rate 125Msps<br />Acquisition Bandwidth 150Mhz<br />Transmission Sample Rate 500Msps<br />
  8. 8. Specs of an SDR platform<br />RF Module:<br />Receiver<br />Frequency range 30Mhz to 900Mhz<br />Switching speed 240us to 420us<br /> Minimum Detectable signal -102dbm<br />Transmitter<br />Frequency Range 200Mhz to 930Mhz<br />Synthesizer Freq Range 500MHz to 930Mhz<br />Switching speed 240us to 420us <br />
  9. 9. FHSS on the SDR board<br />Transmitter:<br />Data Acq<br />Frequency Hopping<br />Up Sampling<br />Up Conversion to IF<br />Modulation<br />DSP<br />FPGA<br />DAC<br />Up Conversion to RF<br />Tx Antenna<br />Data Conv<br />RF Module<br />
  10. 10. FHSS on the SDR board<br />Receiver:<br />FPGA<br />Data Conv<br />RF Module<br />Down Conversion from IF<br />Rx Antenna<br />ADC<br />Down Sampling<br />Down Conversion to IF<br />De-hopping<br />Demodulation<br />Received Data<br />DSP<br />
  11. 11. Hardware Flow Diagram<br />RF Module<br />Tx Antenna<br />Rx Antenna<br />430MHz<br />30 MHz<br />RF Out<br />RF In<br />IF Out<br />IF In<br />30 MHz<br />DAC<br />FPGA Virtex-4<br />Data Conversion Expansion Connector<br />ADC<br />Data Conv Module<br />102.4 MSPS<br />2 MSPS<br />DM6446<br />Virtex-4 SX35 FPGA<br />Data Conversion Expansion Connector<br />VPSS<br />8KSPS<br />DSP Module<br />PCM codecs<br />
  12. 12. Synchronization<br /> Pilot Signal<br />PN Sequence<br />Data<br />
  13. 13. Technical Challenges<br />Less powerful ADC<br />Synchronization<br />Switching Speed 240us<br />Less powerful ADC<br />DAC<br />RF module<br />LYRIO<br />125 MSPs<br />4 MSPs<br />DM6446<br />Virtex-4 SX35 FPGA<br />Modulation Scheme<br />Computational Efficiency<br />Up Sampling<br />Non-integer Up sampling factor<br />VPSS<br />Buffer Length=2^x<br />
  14. 14. Conclusions<br />Successful Simulation of the FHSS system on Matlab<br />Successful Implementation of an FSK transceiver on a Spartan III kit<br />Successful Implementation of a test bench that could take any waveform and implement it<br />Successful Implementation of an FHSS transceiver on the SDR platform<br />A real time audio transceiver on the SDR platform with FSK<br />A real time audio transceiver on the SDR platform with PSK<br />
  15. 15. Recommendations<br />Comparison of a large number of modulation schemes on the developed test bench<br />Source Coding and Channel Coding Algorithms<br />Multi-node Communication<br />
  16. 16. Questions <br />