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# Ece 465 project_1_report_vishesh_shravan

16-bit 3 number designed using two divide and conquer techniques namely:
Wait Strategy
Design for all cases strategy

The implementation for this project was done in the FPGA simulator Quartus

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### Ece 465 project_1_report_vishesh_shravan

1. 1. Digital System Design 16-BIT 3 NUMBER ADDER ECE -465 DIGITAL SYSTEM DESIGN PROJECT-1 Shravan Nagarjun Rangaraj Vishesh Chanana
2. 2. Digital System Design To design an efficient 16bit 3numbers(A,B,D) Full adder circuit and produce 18bit output sum(S). The schematic design has to be done in two different designs. (i) Wait strategy (ii) Design for all case strategy The root problem of 16bit addition of 3numbers is subdivided on it operand size to make the solving easier. Thereby reducing the complexity of the problem. The divide and conquer tree is shown below: Here the 16Bit addition on the top level is the root problem. It gets subdivided at each level till we come till one bit addition. That is performed by FA5 unit. Hence we get 16bit sum(S) with 2carriers (C1 and C2).
4. 4. Digital System Design Assuming the numbers to be added are A,B,D and Carry C1 from the (i-1)th bit and Carry C2 from the (i-2)th bit. The Full adder and half adder will each give a 2-bit output, which must be added together to get the 3 bit output. Hence these two 2-bit numbers are given to a full adder and a half adder to get the sum final sum and two carry output bits.
5. 5. Digital System Design Total number of inputs in 1- FA5 = 5inputs Total input units = 16*FA5 + 1 HA + 1 OR gate = 80+2+2= 84inputs. (i) 16Bit circuit: Delay of 1FA5 = 2FA+1HA (critical path) = 5p+5p+2p=12p Total delay of the 16bit circuit = 16*FA5 + 1HA + 1XOR=160p+2p+2p= 196p. (ii) n-Bit circuit: delay for n-bit 3numbers addition will be n(FA5) + 1 HA + 1 XOR=(12n+4)p (i) 16Bit circuit: 16Fa5+1HA+1XOR=18units (ii) N-bit circuit Total basic components required= n(FA5)+ 1 HA + 1 OR= (n+2)basic units. The numbers A,B and D are added using full adder which will give us S1=1 Car1=1. The Carries C1=1 and C2=1 are separately added which will give us S2=0 Car2=1. Now the S1Car1 must be added with S2Car2. In the Half adder the S1=1 and S2=0 will be added which will give SUM=1 and Car3=0. The Car1=1 and Car2=1 are added in full adder along with Car3=0. This will give us CARRY1=0 and CARRY2=1. That’s the output of FA5
6. 6. Digital System Design The basic unit of FA5 is designed using 2 Full adders and 2 Half adders. The green line shows the critical path of the schematic circuit. The timing simulation is performed for the above design and the waveforms are recorded. The screenshot of the worst case delay(critical path) is shown below. This is also known as propagation delay. There exists minor variation in worst case delay in the outputs of S[16] and S[17] in the order of 1/10th . So its neglected.
7. 7. Digital System Design Propagation delay(Ts) = 25.568ns T = 13.767ns (As defined in the question. Refer the screenshot to verify the correctness) Hence AT2 = 84*13.7672 =15920.94 units. (A is calculated in the previous page)
8. 8. Digital System Design
9. 9. Digital System Design Design for all case strategy is used to reduce the propagation delay significantly. However corresponding units cost gets increased. So to maintain a balance between the least propagation delay and a cost efficient design, up till certain level DAC is implemented and further down its wait strategy. GENERAL EXPLANATION: Unlike Wait Strategy, the sub problem A1 need not wait for the result from the Sub problem A2. As soon as the processing for the sub problem A2 starts, A1 unit also starts processing. But 4 such copies with values for C1 and C2 as 00,01,10,11 takes place. Hence the total time taken for DAC to process will be equal to the timing taken to complete one of the sub problems(since both the sub problems are the same) plus the time of the multiplexer. A single level DAC is shown below: Here we have C1 and C2 from the previous bits. So the (i+1)th bit can have 4 possible combinations of C1,C2. Hence we compute the addition early for each of those combinations of C1 and C2. These 4 values are given to 4x1 Mux. The selector lines for this mux are the C1 and C2 from the nth and (i-1)th bit respectively. Depending on that the values from the sub problem A2 and A1 will be passed to the stitch up functions.
10. 10. Digital System Design As said earlier, in order to reduce the propagation delays as well as to make the circuit cost efficient, we incorporate DAC till certain level and Wait strategy till certain level. Using the formula given, the level J is determined. The group size x= √n Level j = log(n/x opt) = logn−log(x opt) =log (16/4) =log16-log4=4—2=2. Hence we use DAC to the first two level, then wait strategy for the rest of the levels.
11. 11. Digital System Design The 16-bit adder’s design looks like this : The smallest unit of a 16-bit 3 number adder design using the DAC strategy is a 4-bit adder that implements a wait strategy. One 4-bit adder acts as the LSB for each 8-bit block. Four 4-bit adders are needed for the MSB part of each block.
13. 13. Digital System Design (ii) For n-bit 3numbers addition: Delay= x(Delay of FA5)+(n/x -1)(Delay of 4x1 MUX) X=group size. For 16Bit 3numbers addition: Basic units in 1-4B W.S=4FA5+1XOR+1HA=6units Total number of basic units in 16Bit DAC=25*4B W.S+5MUX1 +1MUX2=156units.
14. 14. Digital System Design Two different types of 4x1 multiplexer are used. One with 10input bus node entry and the other with 5input bus node. However the working is still the same. The quartus implementation of 4x1 multiplexer with 5 input bus node is shown below: Similar circuit with 10input bus node is used in the final 16bit addition implementation, as shown below:
16. 16. Digital System Design :
17. 17. Digital System Design :
18. 18. Digital System Design : Propagation delay(Ts) = 18.6233ns T = 15.794ns (As defined in the question. Refer the screenshot to verify the correctness) Hence the AT2 =636*15.794*15.794=158650.65 units
19. 19. Digital System Design
20. 20. Digital System Design It can be seen that the above designed circuits produce proper results for every type of input numbers. From the waveform graph it is clear that the Ts and T are not the same. TYPE T(As defined..)[ns] AT2 Ts[ns] 1.WAIT STRATEGY 13.767 15920.94 units 25.568 2.DAC STRATEGY 15.794 158650.65 units 18.623 From the above table we can conclude that the propagation delay for the DAC strategy is less than that of the Wait strategy, but it comes with a higher cost.

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16-bit 3 number designed using two divide and conquer techniques namely: Wait Strategy Design for all cases strategy The implementation for this project was done in the FPGA simulator Quartus

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