Implementation of page table


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  • If we want to access location i, we must first index into the page table, using the value in the PTBR offset by the page number for ch8/8.This task requires a memory access. It provides us with the frame number which is combined with the page offset to produce the actual address. We can then access the desired place in memory
  • MMU is a computer hardware component responsible for handling accesses to memory requested by the CPU. Its functions include translation of virtual addresses to physical addresses, memory protection, cache control
  • Content-addressable memory (CAM) is a special type of computer memory used in certain very high speed searching applicationsUnlike standard computer memory (random access memory or RAM) in which the user supplies a memory address and the RAM returns the data word stored at that address, a CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it
  • When the associative memory is presented with an item, the item is compared with all keys simultaneously. If the item is found,the corresponding value field is returned
  • -When a logical address is generated by the CPU, its page number is presented to the TLB. If the page number is found , its frame number is immediately available and is used to access memory. The whole task may take less than 10 percent longer than it would if an unmappedmemory reference were used. If the page number is not in the TLB (known as a TLB miss)-In addition, we add the page number and frame number to the TLB, so that they will be found quickly on the next reference.-Some TLBs store address-space identifiers (ASIDs) in each TLB entry. An ASID uniquely identifies each process and is used to provide address-space protection for that process. When the TLB attempts to resolve virtual page numbers, it ensures that the ASID for the currently running process matches the ASID associated with the virtual page. If the ASIDs do not match, the attempt is treated as a TLB miss.-If the TLB is already full of entries, the operating system must select one for replacement. Replacement policies range from least recently used (LRU) to random.-page fault is an interrupt (or exception) to the software raised by the hardware, when a program accesses a page that is mapped in address space, but not loaded in physical memory
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  • in the form of a page-table length register (PTLR), to indicate the size of the page table. This value is checked against every logical address to verify that the address is in the valid range for the process. Failure of this test causes an error trap to the operating system
  • The inverted page table (IPT) combines a page table and a frame table into one data structure at its core is a fixed-size table with the number of rows associating to each frame in memory. If there were 4000 frames, the inverted page table has 4000 rows. For each row there is an entry for the virtual page number (VPN), the physical page number (not the physical address), some other data and a means for creating a collision chain,
  • A simple technique for addressing this issue is to allow the page table to contain only one mapping of a virtual address to the shared physical address. This meansthat references to virtual addresses that are not mapped result in page faults.
  • Implementation of page table

    1. 1. Implementation & Structure of Page Table<br />
    2. 2. Agenda<br />Page Table Definition<br />Implementation of Page Table<br />Hardware Support<br />Paging Hardware With TLB<br />Memory Protection<br />Page Table Structure<br />Hierarchical Paging<br />Shared Pages<br />Inverted Page Tables<br />Hashed Page Tables<br />
    3. 3. Page Table Definition<br />A page table is the data structure<br />used by a virtual memory system<br />in a computer operating system <br />to store the mapping between<br /> virtual addresses and physical<br /> addresses<br />
    4. 4. Two concern to discuss<br />Implementation of Page Table<br />concerning about the access time of page table and load it to main memory<br />Page Table Structure<br /> concerning about the page table size & structure implementation<br />
    5. 5. Implementation of Page Table(Hardware Support)<br />The hardware implementation of the page table can be done in several ways. <br />In the simplest case, the page table is implemented as a set of dedicated registers. These registers should be built with very high-speed logic to make the paging-address translation efficient.<br />Problem with page size…..<br />
    6. 6. Hardware Support<br />Page table is kept in main memory.<br />Page-table base register (PTBR) points to the page table.<br />Page-table length register (PRLR) indicates size of the page table.<br />In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction<br />Problem with access time…..<br />
    7. 7. Paging Hardware With TLB<br />The CPU's memory management unit (MMU) stores a cache of recently used mappings from the operating system's page table. This is called the translation look a side buffer (TLB).<br />
    8. 8. Paging Hardware With TLB<br />The TLB may reside between the CPU and the CPU cache, between the CPU cache and primary storage memory, or between levels of a multi-level cache.<br />The TLB is typically implemented as content-addressable memory (CAM).<br />The TLB is associative, high-speed memory. Each entry in the TLB consists of two parts:<br /> a key (or tag) and a value.<br />
    9. 9. Paging Hardware With TLB<br />Associative memory – parallel search <br />Address translation (A´, A´´)<br />If A´ is in associative register, get frame # out. <br />Otherwise get frame # from page table in memory<br />Page #<br />Frame #<br />
    10. 10. Paging Hardware With TLB<br />TLB Hit<br />TLB Miss<br />If the TLB is already full of entries, the operating system must select one for replacement<br />address-space identifiers (ASIDs)<br />Page fault<br />
    11. 11. Paging Hardware With TLB<br />
    12. 12. Paging Hardware With TLB<br />Effective Access Time<br />Associative Lookup =  time unit<br />Assume memory cycle time is 1 microsecond<br />Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers.<br />Hit ratio = <br />Effective Access Time (EAT)<br /> EAT = (1 + )  + (2 + )(1 – )<br /> = 2 +  – <br />
    13. 13. Paging Hardware With TLB<br />Suppose: <br />TLB lookup takes 5 nano sec. <br />Memory access time is 100 nano sec. <br />Hit ratio (probability to find page number in TLB) is ? <br />Effective Access Time = (5+100)* ? +( 5+100+100)*(1- ?) Suppose ? = 80% (for example, TLB size = 16) <br /> EAT = 105*.8 + 205*.2 = 125 nano sec. <br /> Suppose ? = 98% (for example, TLB size = 64) <br /> EAT = 105*.98 + 205*.02 = 107 nano sec<br />
    14. 14. Memory Protection<br />Memory protection implemented by associating protection bit with each frame.<br />-One bit can define a page to be read-Write or read-only<br />Valid-invalid bit attached to each entry in the page table:<br />“valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page.<br />“invalid” indicates that the page is not in the process’ logical address space.<br />page-table length register (PTLR), to indicate the size of the page table.<br />
    15. 15. Memory Protection<br />
    16. 16. Page Table Structure<br />Most modern computer systems support a large logical address space(2^32 to 2^64). In such an environment, the page table itself becomes excessively large. For example, consider a system with a 32-bit logical address space. If the page size in such a system is 4 KB (212 ), then a page table may consist of up to 1 million entries (2^32/2^12). Assuming that each entry consists of 4 bytes, each process may need up to 4 MB of physical address space for the page table alone.<br />
    17. 17. Hierarchical Page Tables<br />Knowing as Multilevel Paging<br />The page table might be too big to fit in a contiguous space, so we may have a hierarchy with several levels<br />Break up the logical address space into multiple page tables.<br />A simple technique is a two-level page table, three-level page table.<br />
    18. 18. Two-Level Page-Table Scheme<br />
    19. 19. Two-Level Paging Example<br />A logical address (on 32-bit machine with 4K page size) is divided into:<br />a page number consisting of 20 bits.<br />a page offset consisting of 12 bits.<br />Since the page table is paged, the page number is further divided into:<br />a 10-bit page number. <br />a 10-bit page offset.<br />Thus, a logical address is as follows:where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table.<br />page number<br />page offset<br />p2<br />pi<br />d<br />10<br />12<br />10<br />
    20. 20. Three-Level Paging Example<br />A logical address (on 64-bit machine with 4K page size) is divided into:<br />The next step Would be a four-level paging scheme,<br />
    21. 21. Address-Translation Scheme<br />Address-translation scheme for a two-level 32-bit paging architecture<br />
    22. 22. Performance of Hierarchical Paging<br />Suppose: <br />Three level paging <br />TLB lookup takes 5 nano sec. <br />Memory access time is 100 nano sec. <br />Hit ratio (probability to find page number in TLB) is ? <br />Effective Access Time = (5+100)* ? +( 5+300+100)*(1- ?) Suppose ? = 80% (for example, TLB size = 16) <br /> -EAT = 105*.8 + 405*.2 = 165 nano sec. Suppose ? = 98% (for example, TLB size = 64) <br /> -EAT = 105*.98 + 405*.02 = 111 nano sec.<br />
    23. 23. Shared Pages<br />Shared code<br />One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). <br />Shared code must appear in same location in the logical address space of all processes.<br />Private code and data <br />Each process keeps a separate copy of the code and data.<br />The pages for the private code and data can appear anywhere in the logical address space.<br />
    24. 24. Shared Pages Example<br />
    25. 25. Inverted Page Table<br />The inverted page table (IPT) combines a page table and a frame table into one data structure.<br />One entry for each virtual page number & real page of memory.<br />Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page.<br />Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.<br />
    26. 26. Inverted Page Table<br />Use hash table to limit the search to one — or at most a few — page-table entries.<br />Say goodbye to sharing ? <br /> -because there is only one virtual page entry for every physical page, one physical page cannot have two (or more) shared virtual addresses.<br />
    27. 27. Inverted Page Table Architecture<br />
    28. 28. Hashed Page Tables<br />Common in address spaces > 32 bits.<br />The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.<br />Each element consists of three fields: <br />(1) the virtual page number,<br />(2) the value of the 111apped page frame,<br /> (3) a pointer to the next element in the linked list.<br />Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.<br />
    29. 29. Hashed Page Table<br />
    30. 30. THANK YOU<br />