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  1. 1. Design and Synthesis of Image Processing Systems using Reconfigurable Dataflow Graphs Mainak Sen and Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies University of Maryland at College Park Maryland DSPCAD Research Group November 22, 2005 Leiden University, The Netherlands
  2. 2. Outline <ul><li>Dataflow-based model of computation for modeling the behavior of DSP applications </li></ul><ul><li>Decidable dataflow models </li></ul><ul><ul><li>Example: use of decidable dataflow as a model of computation for modeling the mapping of (decidable) dataflow behaviors onto embedded multiprocessors </li></ul></ul><ul><li>Structured reconfiguration of dataflow graphs </li></ul><ul><li>Examples of meta-modeling techniques that can be classified as structured, reconfigurable dataflow </li></ul><ul><ul><li>Parameterized dataflow and its application to SDF </li></ul></ul><ul><ul><li>Homogeneous-parameterized dataflow and its application to SDF and CSDF </li></ul></ul><ul><ul><li>Experiments on a gesture recognition application </li></ul></ul><ul><li>Summary </li></ul>
  3. 3. Dataflow-based design for DSP (Example from Agilent ADS tool)
  4. 4. DSP-oriented Dataflow Models of Computation <ul><li>Used widely in design tools for DSP </li></ul><ul><li>Application is modeled as a directed graph </li></ul><ul><ul><li>Nodes (actors) represent functions </li></ul></ul><ul><ul><li>Edges represent communication channels between functions </li></ul></ul><ul><ul><li>Nodes produce and consume data from edges </li></ul></ul><ul><ul><li>Edges buffer data in FIFO (first-in first-out) fashion </li></ul></ul><ul><li>Data-driven execution model </li></ul><ul><ul><li>A node can execute whenever it has sufficient data on its input edges </li></ul></ul><ul><ul><li>The order in which nodes execute is not part of the specification </li></ul></ul><ul><ul><li>The order is typically determined by the compiler, the hardware, or both </li></ul></ul><ul><li>Iterative execution </li></ul><ul><ul><li>Body of loop to be iterated a large or infinite number of times </li></ul></ul>
  5. 5. Dataflow Features and Advantages <ul><li>Exposes coarse-grain parallelism. </li></ul><ul><li>Exposes high-level structure that facilitates analysis, verification, and optimization. </li></ul><ul><li>Captures multi-rate behavior. </li></ul><ul><li>Complementary to ongoing advances in DSP compiler technology for procedural languages, such as C and MATLAB. </li></ul><ul><li>Encourages desirable software engineering practices: modularity and code reuse </li></ul><ul><ul><li>Amenable also to aspect-oriented design. </li></ul></ul><ul><li>Intuitive to DSP algorithm designers: signal flow graphs. </li></ul>
  6. 6. Evolution of Dataflow Models for DSP <ul><li>Synchronous dataflow: static multirate behavior </li></ul><ul><ul><li>Agilent ADS, Cadence SPW, etc. </li></ul></ul><ul><li>Well-behaved dataflow: schemas for bounded dynamics </li></ul><ul><li>Boolean/integer dataflow: Turing complete models </li></ul><ul><li>Multidimensional synchronous dataflow: image and video </li></ul><ul><li>Scalable synchronous dataflow: block processing </li></ul><ul><ul><li>Synopsys COSSAP </li></ul></ul><ul><li>Cyclo-static dataflow: phased behavior </li></ul><ul><ul><li>Synopsys El Greco, Eonic Systems Virtuoso Synchro, System Canvas </li></ul></ul><ul><li>Bounded dynamic dataflow : bounded dynamics </li></ul><ul><li>The processing graph method: reconfigurable dynamic DF </li></ul><ul><ul><li>US Naval Research Laboratory, MCCI Autocoding Toolset </li></ul></ul><ul><li>Parameterized dataflow: dynamically-reconfigurable static DF </li></ul><ul><li>Blocked dataflow: image and video in terms of reconfigurable dataflow </li></ul>
  7. 7. Modeling Design Space (Third dimension: simplicity and intuitive appeal) E x p r e s s i v e p o w e r Verification / synthesis power X C, BDF, DDF X SDF X CSDF X CSDF, SSDF MDSDF, WBDF X X PSDF X PCSDF
  8. 8. Decidable Dataflow Models <ul><li>Modeling flow for representing static flowgraph behavior: </li></ul><ul><ul><li>Cyclo-static dataflow (CSDF), multiphase modeling  </li></ul></ul><ul><ul><li>Synchronous dataflow (SDF), multirate modeling  </li></ul></ul><ul><ul><li>Homogeneous synchronous dataflow (HSDF)  </li></ul></ul><ul><ul><li>Acyclic homogeneous synchronous dataflow (“task graphs”) </li></ul></ul><ul><li>These are in decreasing order or generality </li></ul><ul><li>Designs represented in the more general models can be converted to equivalent representations in the less general ones </li></ul><ul><ul><li>e.g., CSDF  SDF  HSDF  task graph </li></ul></ul><ul><li>HSDF: each actor (graph node) produces/consumes exactly one data value to/from each incident output/input edge </li></ul><ul><ul><li>Suitable for exposing parallelism </li></ul></ul><ul><ul><li>Not the best model for minimizing memory requirements </li></ul></ul>
  9. 9. Synthesis Techniques for Decidable Models <ul><li>Static scheduling: low overhead, predictability </li></ul><ul><li>Performance analysis through synchronization graphs </li></ul><ul><li>Loop scheduling </li></ul><ul><ul><li>Implicit repetition in the dataflow graph (through changes in sample rate) needs to be translated into explicit repetition in the form of loops on the execution target. </li></ul></ul><ul><ul><li>Complex design space exists for such translation </li></ul></ul><ul><ul><li>Complementary to procedural language techniques for nested loop compilation </li></ul></ul><ul><li>Loop scheduling techniques </li></ul><ul><ul><li>Simulation speedup (minimization of scheduling complexity) </li></ul></ul><ul><ul><li>Code/data minimization </li></ul></ul><ul><ul><li>Hierarchical parallel scheduling </li></ul></ul><ul><ul><li>Block processing </li></ul></ul><ul><li>Task scheduling for latency/throughput optimization </li></ul><ul><li>Probabilistic design: exploiting tolerances to deadline misses </li></ul>
  10. 10. Example: Intermediate representations for synthesis from decidable dataflow models <ul><li>Consider a decidable dataflow behavior that is to be implemented on a self-timed, embedded multiprocessor </li></ul><ul><ul><li>Natural way to implement DSP multiprocessors from decidable dataflow </li></ul></ul><ul><ul><li>Actor assignment and ordering are performed statically </li></ul></ul><ul><ul><li>Invocation (dispatch) of actors is performed dynamically, through synchronization </li></ul></ul><ul><li>Candidate mappings of the behavior onto the architecture can be represented through an intermediate representation that also has decidable dataflow semantics </li></ul><ul><ul><li>This representation is useful for understanding the performance, communication overhead, and synchronization structure associated with the candidate mapping </li></ul></ul><ul><li>Facilitates the separation of communication and synchronization functionality </li></ul><ul><li>This is a useful modeling methodology for design space exploration </li></ul>
  11. 11. Interprocessor Communication Graph ( G ipc ) Self-timed schedule and its IPC graph 2r 1 4s 1 4s 2 4s 3 5s 1 7r 1 8r 1 9r 1 6 2 3 4 5 8 7 9 1 IPC Graph Every edge ( v i , v j ) induces the precedence constraint 2 4 1 3 6 5 8 7 9 Self-Timed Schedule Proc 1: (1, 2, 3, 4, 6) Proc 2: (5, 7, 8) Proc 3: (9) Proc 1 Proc 2 Proc 3
  12. 12. The synchronization graph G s <ul><li>Derived from the interprocessor communication graph </li></ul><ul><li>Synchronization edges are distinguished from interprocessor communication (IPC) edges </li></ul><ul><ul><li>Synchronization edges represent precedence constraints that are enforced by synchronization protocols </li></ul></ul><ul><ul><li>IPC edges represent data transfers </li></ul></ul><ul><li>Interprocessor connections </li></ul><ul><ul><li>Coincident synchronization and IPC edges  communication together with synchronization protocol (conventional approach) </li></ul></ul><ul><ul><li>IPC edge only  communication without synch. protocol </li></ul></ul><ul><ul><li>Synchronization edge only  synchronization protocol only </li></ul></ul>
  13. 13. Applications of Synchronization Graphs <ul><li>Simulation </li></ul><ul><li>Throughput estimation through cycle mean analysis </li></ul><ul><li>Removal of redundant synchronizations </li></ul><ul><li>Resynchronization </li></ul><ul><li>Conversion to more efficient synchronization protocols (strongly connected synchronization graphs) </li></ul><ul><li>Statically determining and minimizing the sizes of interprocessor communication buffers </li></ul><ul><li>All are post-processing methods that can be applied to improve a wide range of existing task graph scheduling techniques on a wide range of multiprocessor architectures. </li></ul><ul><li>These techniques benefit from good execution time estimates, but do not depend on exact execution time values to deliver useful results. </li></ul>
  14. 14. Beyond Decidable Models <ul><li>Limited expressive power: DSP applications increasingly employ high-level dynamics in their behavior </li></ul><ul><ul><li>User interface functionality </li></ul></ul><ul><ul><li>Mode changes </li></ul></ul><ul><ul><li>Adaptive algorithms </li></ul></ul><ul><ul><li>Reconfiguration of processing resources/parameters </li></ul></ul><ul><li>However, key subsystems still exhibit large amounts of “quasi-static” structure --- structure that stays fixed across significant windows of time. </li></ul><ul><li>Various dynamic dataflow models have been proposed that address the limitation above by abandoning most or all restrictions related to decidable dataflow </li></ul><ul><li>However, these methods are correspondingly limited in their ability to exploit the quasi-static structure described above </li></ul>
  15. 15. Parameterized Dataflow: Structured Control of Dynamic Parameters <ul><li>The Key discipline that is imposed on reconfiguration is that each subsystem must have a consistent view of each of its actors (hierarchical or primitive) throughout any given iteration of that subsystem. </li></ul>
  16. 16. Parameterized Dataflow <ul><li>Hierarchical modeling </li></ul>subsystem parent graph subinit init body parameter n, ... writes n reads n <ul><li>Parameterized DF subsystem is composed of 3 parmeterized DF graphs: </li></ul><ul><ul><li>init , subinit , body </li></ul></ul><ul><li>Subsystem parameters </li></ul><ul><ul><li>configured in init/subinit, used in body </li></ul></ul><ul><li>Dynamically reconfigurable </li></ul>
  17. 17. Meta-modeling with parameterized dataflow <ul><li>Parameterized dataflow can be applied to any dataflow model of computation (“base model”) to augment that model with dynamic reconfiguration capabilities in a structured way </li></ul><ul><ul><li>Provides for efficient quasi-static scheduling </li></ul></ul><ul><ul><li>Enables execution to be viewed in terms of a sequence of dataflow graphs in the base model </li></ul></ul><ul><li>Parameterized dataflow + XYZ  “Parameterized XYZ” </li></ul><ul><li>Examples of parameterized dataflow models of computation that we are developing and experimenting with </li></ul><ul><ul><li>parameterized synchronous dataflow (PSDF) </li></ul></ul><ul><ul><li>parameterized cyclo-static dataflow (PCSDF) </li></ul></ul>
  18. 18. Parameterized Synchronous Dataflow (PSDF) <ul><li>“Locally synchrony” conditions can be formulated and checked in a quasi-static fashion to ensure that bounded token production and consumption along with bounded delays lead to bounded memory requirements overall. </li></ul><ul><ul><li>This is not true of unstructured dynamic dataflow models, such as general dynamic dataflow, boolean dataflow, and bounded dynamic dataflow </li></ul></ul><ul><li>Techniques for construction of streamlined looped schedules for synchronous dataflow graphs have natural and efficient extensions to the construction of parameterized looped schedules for PSDF graphs. </li></ul>
  19. 19. PSDF Example: CD to DAT Conversion initChild setFac (sets i 1 ,… d 4 ) CD PF1 1 1 d 1 i 4 i 1 i 3 d 2 d 4 i 2 d 3 PF2 preamble PF3 PF4 DAT params i 1 , d 1 , …., i 4 , d 4 init body body repeat 5 times { fire setFac /* sets i 1 , d 1 , i 2 , d 2 , i 3 , d 3 , i 4 , d 4 */ int _ g 1 = gcd( i 1 , d 2 ); int _ g 2=gcd(( i 2 x i 1 ) / _ g 1, d 3 ) int _ g 3=gcd(( i 3 x i 2 x i 1 ) / (_ g 2 x _ g 1), d 4 ); repeat ( d 4 / _ g 3) times { repeat ( d 3 / _ g 2) times { repeat ( d 2 / _ g 1) times { repeat ( d 1 ) times {fire CD } fire PF1 } repeat ( i 1 / _ g 1) times {fire PF2 } } repeat (( i 2 x i 1 ) / (_ g 2 x _ g 1)) times {fire PF3 } } repeat (( i 3 x i 2 x i 1 ) / (_ g 3 x _ g 2 x _ g 1)) times { fire PF4 } repeat ( i 4 ) times {fire DAT } }
  20. 20. PSDF Example: Speech Compression
  21. 21. PCSDF Version of Speech Compression
  22. 22. Outline <ul><li>Dataflow-based model of computation for modeling the behavior of DSP applications </li></ul><ul><li>Decidable dataflow models </li></ul><ul><ul><li>Example: use of decidable dataflow as a model of computation for modeling the mapping of (decidable) dataflow behaviors onto embedded multiprocessors </li></ul></ul><ul><li>Structured reconfiguration of dataflow graphs </li></ul><ul><li>Examples of meta-modeling techniques that can be classified as structured, reconfigurable dataflow </li></ul><ul><ul><li>Parameterized dataflow and its application to SDF </li></ul></ul><ul><ul><li>Homogeneous-parameterized dataflow and its application to SDF and CSDF </li></ul></ul><ul><ul><li>Experiments on a gesture recognition application </li></ul></ul><ul><li>Summary </li></ul>
  23. 23. Homogeneous Parameterized Dataflow (HPDF) <ul><li>Parameterized dataflow model that can encapsulate dynamicity of application. </li></ul><ul><li>Meta-modeling technique. Hierarchical actors can have any other underlying dataflow model (SDF, CSDF, PSDF etc.) </li></ul><ul><li>Data production & consumption rates though dynamic are equal across an edge for a large number of applications - thus the name homogeneous. </li></ul><ul><li>Reconfiguration can be performed without introducing hierarchy when more natural to do so (advantage over parameterized dataflow). </li></ul><ul><li>Parameterized dataflow is a more powerful technique and thus can be used to represent a wider set of applications. </li></ul>
  24. 24. Applications <ul><li>Applications with dynamic run-time data and aggregated final-stage processes perform especially well for HPDF over SDF semantics. </li></ul><ul><li>Many applications in image and speech processing seem well suited for our model. </li></ul><ul><li>We applied the model on two applications – </li></ul><ul><li>- A real-time video processing algorithm for smart camera developed at Princeton </li></ul><ul><li>- A face detection algorithm developed at CFAR labs in UMD. </li></ul>
  25. 25. Application characteristics <ul><li>This structure seems to be abundant in many audio/video applications. </li></ul><ul><li>Our HPDF model is a natural fit for applications with the above structure. </li></ul>A B M N Dynamic but balanced amount of data Aggregating final-stage
  26. 26. Gesture recognition algorithm <ul><li>Real-time video processing for gesture recognition. </li></ul><ul><li>Does low-level (red oval) and high-level processing. </li></ul><ul><li>Low-level processing recognizes body parts and identifies movements. </li></ul><ul><li>High-level processing recognized actions. </li></ul><ul><li>We concentrate on low-level processing. </li></ul>Ref : W. Wolf, B. Ozer, T. LV. Smart cameras as embedded systems. IEEE Computer Magazine Vol 35, Iss 9, Sept 2002, Pages 48-53
  27. 27. HPDF model of gesture recognition algorithm Dynamic data Aggregating final-stage Dynamic data n n p p Ptolemy II implementation Region finding Contour following Ellipse Fitting Graph Matching
  28. 28. Modeling with HPDF/CSDF VIDEO INPUT REGION EXTRACTION CONTOUR FOLLOWING (s 1) (s 1) (s 1) (s 1) (s 1) (s 1) (s 1) (X i , Y i ) (s 1) (X i , Y i ) ELLIPSE FITTING ( I 0 ,I k i ) (n 1) MATCH p (p i 1, q i 0) p phases with 1 token and (n-p) phases with 0 token production #phases = #pixels = s
  29. 29. Integrating HPDF and CSDF <ul><li>Number of phases in a fundamental period can vary dynamically. </li></ul><ul><li>Number of tokens produced or consumed in a given phase can also vary dynamically. </li></ul><ul><li>HPDF constraint: the total number of tokens produced by a source actor of a given edge in a given invocation (a fundamental period) must equal the total number of tokens consumed by the sink in its corresponding invocation. </li></ul>
  30. 30. <ul><li>Each frame has 384x240 pixels, so we model the input as a CSDF actor with 92160 = s phases. </li></ul><ul><li>Model captures pixel level parallelism present in Region. </li></ul><ul><li>It also captures the frame level parallelism through the number of phases in Input (s). </li></ul>Finer granularity and Input modeling VIDEO INPUT REGION EXTRACTION (s 1) (s 1) (s 1) (s 1) (s 1) (s 1) #phases = #pixels = s
  31. 31. Modeling dynamicity - Contour <ul><li>2 phases for Contour </li></ul><ul><li>First one scans until finds a contour. </li></ul><ul><ul><li>Output = 0 tokens </li></ul></ul><ul><li>Second one follows this contour and all the overlapping ones. </li></ul><ul><ul><li>Output = k i tokens, each token is a list of pixels from a contour </li></ul></ul><ul><li>Homogeneous condition remains: </li></ul><ul><li>=s </li></ul>
  32. 32. Scheduling <ul><li>VRCEM </li></ul><ul><li>(s V)(s R)(2 I C)(n E)M </li></ul><ul><li>(s VR)(2 I C)(n E)M </li></ul>
  33. 33. <ul><li>We applied HPDF to successfully model a face detection algorithm also. </li></ul><ul><li>We developed a TI DSP implementation of the HPDF model of the gesture recognition algorithm. </li></ul><ul><li>The application was run on a TMS320C64xx fixed point processor. </li></ul><ul><li>When implemented with our HPDF model, the runtime was 21405671 cycles. </li></ul><ul><li>With a 40ns cycle period, execution time for the application was 0.86 sec. </li></ul>Results
  34. 34. Results (contd.) <ul><li>Scheduling overhead was minimal as imperatively highly streamlined quasi-static schedule was obtained. </li></ul><ul><li>Worst case buffer size 642 Kb when the input images were 384X240 pixels. HPDF modeling suggested buffer reuse between the edges. </li></ul><ul><li>Original C code had runtime of 27741882 cycles, execution time was 1.11 sec with the same clock period of 40 ns. </li></ul><ul><li>HPDF improved runtime by 23%. </li></ul><ul><li>Efficient hardware code generation is being looked into using hardware synthesis framework developed in our research group. </li></ul>
  35. 35. Summary <ul><li>Dataflow-based model of computation for is attractive for modeling the behavior of DSP applications </li></ul><ul><li>Decidable dataflow models are useful for exposing and exploiting static structure in synthesis tools for DSP </li></ul><ul><li>Decidable dataflow models in conjunction with structured reconfigurable techniques allow for efficient handling of application dynamics </li></ul><ul><li>Examples of structured, reconfigurable dataflow techniques that we discussed: </li></ul><ul><ul><li>Parameterized dataflow and its application to SDF </li></ul></ul><ul><ul><li>Homogeneous-parameterized dataflow and its application to SDF and CSDF </li></ul></ul><ul><ul><li>Experiments on a gesture recognition application </li></ul></ul><ul><li>Other examples include dynamic configuration of graph topologies, and blocked dataflow modeling. </li></ul>
  36. 36. References <ul><li>B. Bhattacharya and S. S. Bhattacharyya. Parameterized dataflow modeling for DSP systems. IEEE Transactions on Signal Processing , 49(10):2408-2421, October 2001 </li></ul><ul><li>S. S. Bhattacharyya, R. Leupers, and P. Marwedel. Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing , 47(9):849-875, September 2000. </li></ul><ul><li>G. Bilsen, M. Engels, R. Lauwereins, and J. A. Peperstraete. Cyclo-static dataflow. IEEE Transactions on Signal Processing , 44(2):397-408, February 1996. </li></ul><ul><li>D. Ko and S. S. Bhattacharyya. Dynamic configuration of dataflow graph topology for DSP system design. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing , pages V-69-V-72, Philadelphia, Pennsylvania, March 2005. </li></ul><ul><li>E. A. Lee and D. G. Messerschmitt. Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Transactions on Computers , February 1987. </li></ul><ul><li>S. Neuendorffer and E. Lee. Hierarchical reconfiguration of dataflow models. In Proceedings of the International Conference on Formal Methods and Models for Codesign , June 2004. </li></ul><ul><li>M. Sen, S. S. Bhattacharyya, T. Lv, and W. Wolf. Modeling image processing systems with homogeneous parameterized dataflow graphs. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing , pages V-133-V-136, Philadelphia, Pennsylvania, March 2005 </li></ul>