382 CHAPTER 10 MEMORY INTERFACE
49. When DRAM is refreshed, can it be done while other sections of the memory operate?
50. If a 1M x 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more
than ____ of time must pass before another row is refreshed.
51. Where is the memory address applied to the 82C08 DRAM controller?
Basic I/O Interface
52. What is the purpose of the BS pin on the 82C08?
53. What is normally connected to the WR pin of the 82C08?
A microprocessor is great at solving problems, but if it can't communicate with the outside
world, it is of little worth. This chapter outlines some of the basic methods of communications,
both serial and parallel, between humans or machines and the microprocessor.
In this chapter, we first introduce the basic I/O interface and discuss decoding for I/O de-
vices. Then, we provide detail on parallel and serial interfacing, both of which have a variety of
applications. As applications, we connect analog-to-digital and digital-to-analog converters, as
well as both DC and stepper motors to the microprocessor.
Upon completion of this chapter, you will be able to:
1. Explain the operation of the basic input and output interfaces.
2. Decode an 8-, 16, and 32-bit I/O device so that they can be used at any I/O port address.
3. Define handshaking and explain how to use it with I/O devices.
4. Interface and program the 82C55 programmable parallel interface.
5. Interface LCD displays, LED displays, keyboards, ADC, DAC, and various other devices
6. Interface and program the 8279 programmable keyboard/display controller.
7. Interface and program the 16550 serial communications interface adapter.
8. Interface and program the 8254 programmable interval timer.
9. Interface an analog-to-digital converter and a digital-to-analog converter to the microprocessor.
10. Interface both DC and stepper motors to the microprocessor.
INTRODUCTION TO I/O INTERFACE
In this section of the text, we explain the operation of the I/O instructions (IN, INS, OUT, and
OUTS). We also explain the concept of isolated (sometimes called direct or I/O mapped I/O) and
memory-mapped I/O, the basic input and output interfaces, and handshaking. A working knowledge
384 CHAPTER 11 BASIC I/O INTERFACE 11-1 INTRODUCTION TO I/O INTERFACE 385
of these topics will make it easier to understand the connection and operation of the programmable The address connections above A15 are undefined for an I/O instruction. The 16-bit variable
interface components and I/O techniques presented in the remainder of this chapter and text. port number (DX) appears on address connection A15-AO. This means that the first 256 I/O
port addresses (OOH-FFH) are accessed by both the fixed and variable I/O instructions, but any
I/O Instructions I/O address from 0100H-FFFFH is only accessed by the variable I/O address. In many dedi-
The instruction set contains one type of instruction that transfers information to an I/O device cated task systems, only the rightmost eight bits of the address are decoded, thus reducing the
(OUT) and another to read information from an I/O device (IN). Instructions (INS and OUTS, amount of circuitry required for decoding. In a PC computer, all 16 address bus bits are de-
found on all versions except the 8086/8088) are also provided to transfer strings of data between coded with locations OOOOH-03XXH, which are the I/O addresses used for I/O inside the PC
the memory and an I/O device. Table 11-1 lists all versions of each instruction found in the mi- for the ISA (industry standard architecture) bus.
croprocessor's instruction set. The INS and OUTS instructions address an I/O device by using the DX register, but do not
Both the IN and OUT instructions transfer data between an I/O device and the micro- transfer data between the accumulator and the I/O device as IN and OUT. Instead, these instruc-
processor's accumulator (AL, AX, or EAX). The I/O address is stored in register DX as a 16-bit tions transfer data between memory and the I/O device. The memory address is located by ES:DI
I/O address or in the byte (p8) immediately following the opcode as an 8-bit I/O address. Intel for the INS instruction and by DS:SI for the OUTS instruction. As with other string instructions,
calls the 8-bit form (p8) a fixed address because it is stored with the instruction, usually in a the contents of the pointers are incremented or decremented, as dictated by the state of the direc-
ROM. The 16-bit I/O address in DX is called a variable address because it is stored in a DX, tion flag (DF). Both INS and OUTS can be prefixed with the REP prefix, allowing more than one
and then used to address the I/O device. Other instructions that use DX to address I/O are the INS byte, word, or doubleword to be transferred between I/O and memory.
and OUTS instructions.
Whenever data are transferred by using the IN or OUT instruction, the I/O address, often Isolated And Memory-Mapped I/O
called a port number (or simply port), appears on the address bus. The external I/O interface de-
codes the port number in the same manner that it decodes a memory address. The 8-bit fixed port There are two different methods of interfacing I/O to the microprocessor: isolated I/O and
number (p8) appears on address bus connections A7-AO with bits A15-A8 equal to 000000002. memory-mapped I/O. In the isolated I/O scheme, the IN, INS, OUT, and OUTS instructions
transfer data between the microprocessor's accumulator or memory and the I/O device. In the
memory-mapped I/O scheme, any instruction that references memory can accomplish the
TABLE 11-1 Input/output instructions. transfer. Both isolated and memory-mapped I/O are in use, so both are discussed in this text.
Isolated I/O. The most common I/O transfer technique used in the Intel microprocessor-based
Instruction Data Width Function
system is isolated I/O. The term isolated describes how the I/O locations are isolated from the
IN AL, p8 8 A byte is input from port p8 into AL memory system in a separate I/O address space. (Figure 11-1 illustrates both the isolated and
IN AX, p8 16 A word is input from port p8 into AX memory-mapped address spaces for any Intel 80X86 or Pentium-Pentium II microprocessor.)
The addresses for isolated I/O devices, called ports, are separate from the memory. Because the
IN EAX, p8 32 A doubleword is input from port p8 into EAX
ports are separate, the user can expand the memory to its full size without using any of memory
IN AL,DX 8 A byte is input from the port addressed by DX into AL space for I/O devices. A disadvantage of isolated I/O is that the data transferred between I/O and
IN AX,DX 16 A word is input from the port addressed by DX into AX the microprocessor must be accessed by the IN, INS, OUT, and OUTS instructions. Separate
IN EAX.DX 32 A word is input from the port addressed by DX into EAX control signals for the I/O space are developed (using M/IO and W/R), which indicate an I/O
INSB 8 A byte is input from the port addressed by DX into the extra segment read (IORC) or an I/O write (IOWC) operation. These signals indicate that an I/O port address,
memory location addressed by Dl, then Dl = Dl ± 1 which appears on the address bus, is used to select the I/O device. In the personal computer, iso-
I NSW 16 A word is input from the port addressed by DX into the extra segment lated I/O ports are used for controlling peripheral devices. An 8-bit port address is used to access
memory location addressed by Dl, then Dl = Dl ± 2 devices located on the system board, such as the timer and keyboard interface, while a 16-bit port
INSD 32 A doubleword is input from the port addressed by DX into the extra segment is used to access serial and parallel ports as well as video and disk drive systems.
memory location addressed by Dl, then Dl ± 4
Memory-Mapped I/O. Unlike isolated I/O, memory-mapped I/O does not use the IN, INS,
OUT p8,AL 8 A byte is output from AL to port p8 OUT, or OUTS instructions. Instead, it uses any instruction that transfers data between the mi-
OUT p8,AX 16 A word is output from AX to port p8 croprocessor and memory. A memory-mapped I/O device is treated as a memory location in the
OUT p8,EAX 32 A doubleword is output from EAX to port p8 memory map. The main advantage of memory-mapped I/O is that any memory transfer instruc-
OUT DX,AL 8 A byte is output from AL to the port addressed by DX tion can be used to access the I/O device. The main disadvantage is that a portion of the memory
OUT DX,AX 16 A word is output from AX to the port addressed by DX system is used as the I/O map. This reduces the amount of memory available to applications. An-
OUT DX,EAX 32 A doubleword is output from EAX to the port addressed by DX other advantage is that the IORC and IOWC signals have no function in a memory-mapped I/O
system and may reduce the amount of circuitry required for decoding.
OUTSB 8 A byte is output from the data segment memory location addressed by SI to
the port addressed by DX, then SI = SI ± 1
OUTSW 16 A word is output from the data segment memory locations addressed by SI to
Personal Computer I/O Map
the port addressed by DX, then SI = SI ± 2 The personal computer uses part of the I/O map for dedicated functions. Figure 11-2 shows the
OUTSD 32 A doubleword is output from the data segment memory locations addressed I/O map for the PC. Note that I/O space between ports OOOOH and 03FFH are normally reserved
by SI to the port addressed by DX, then SI = SI ± 4 for the computer system and the ISA bus. The I/O ports located at 0400H-FFFFH are generally
available for user applications, main-board functions, and the PCI bus. Note that the 80287 arith-
11-1 INTRODUCTION TO I/O INTERFACE 387
386 CHAPTER 11 BASIC I/O INTERFACE
FIGURE 11-2 The I/O map FFFF
FIGURE 11-1 The memory Memory of a personal computer illus-
and I/O maps for the 8086/ I trating many of the fixed I/O I/O Expansion area
8088 microprocessors, areas.
(a) Isolated I/O (b) Memory-
IM x 8 FFFF
64K x 0400
03F8 COM 1
03FO Floppy disk
03DO CGA adapter
Memory + I/O 037F
FFFFF 0378 LPT1
0320 Hard disk
02 F8 COM2
(b) 0020 Interrupt controller
metic coprocessor uses I/O address OOF8H-OOFFH for communications. For this reason, Intel re- 0000 DMA controller
serves I/O ports OOFOH-OOFFH. The 80386-Pentium II use I/O ports 800000F8-800000FFH for
communications to their coprocessors. The I/O ports located between OOOOH and OOFFH are ac-
cessed via the fixed port I/O instructions; the ports located above OOFFH are accessed via the When the microprocessor executes an IN instruction, the I/O port address is decoded
variable I/O port instructions. to generate the logic 0 on SEL. A 0 placed on the output control inputs (1G and 2G) of the
74ALS244 buffer causes the data input connections (A) to be connected to the data output (Y) con-
Basic Input and Output Interfaces nections. If a logic 1 is placed on the output control inputs of the 74ALS244 buffer, the device enters
The basic input device is a set of three-state buffers. The basic output device is a set of data the three-state high-impedance mode that effectively disconnects the switches from the data bus.
latches. The term IN refers to moving data from the I/O device into the microprocessor and the This basic input circuit is not optional and must appear any time that input data are inter-
term OUT refers to moving data out of the microprocessor to the I/O device. faced to the microprocessor. Sometimes it appears as a discrete part of the circuit, as shown in
.| Figure 11-3; sometimes it is built into a programmable I/O device.
The Basic Input Interface. Three-state buffers are used to construct the 8-bit input port 16- or 32-bit data can also be interfaced to various versions of the microprocessor, but this
in Figure 11-3. The external TTL data (simple toggle switches in this example) are is not nearly as common as using 8-bit data. To interface 16 bits of data, the circuit in Figure
the inputs of the buffers. The outputs of the buffers connect to the data bus. The exact data 11-3 is doubled to include two 74ALS244 buffers that connect 16 bits of input data to the 16-bit
connections depend on the version of the microprocessor. For example, the 8088 has data data bus. To interface 32 bits of data, the circuit is expanded by a factor of 4.
connections D7-DO, the 80486 has D31-DO, and the Pentium-Pentium II have D63-DO.
cuit of Figure 11-3 allows the microprocessor to read the contents of the 8 switches that The Basic Output Interface. The basic output interface receives data from the microprocessor
to any 8-bit section of the data bus when the select signal SEL becomes a logic 0. Thus, and must usually hold it for some external device. Its latches or flip-flops, like the buffers found
the IN instruction executes, the contents of the switches are copied into the AL register. in the input device, are often built into the I/O device.
388 CHAPTER 11 BASIC I/O INTERFACE 11-1 INTRODUCTION TO I/O INTERFACE 389
FIGURE 11-3 The basic vc)C are only present on the data bus for less than 1.0 }is. Without a latch, the viewer would never see
input interface illustrating the c) the LEDs illuminate.
connection of eight switches. When the OUT instruction executes, the data from AL, AX, or EAX are transferred to the
Note that the 74ALS244 is a 1111111 latch via the data bus. Here, the D inputs of a 74ALS374 octal latch are connected to the data bus
three-state that controls the 6£ 4 3 2 1 0 9 to capture the output data, and the Q outputs of the latch are attached to the LEDs. When a Q
application of the switch data output becomes a logic 0, the LED lights. Each time that the OUT instruction executes, the SEL
to the data bus. >>>>>>>> 10K
signal to the latch activates, capturing the data output to the latch from any 8-bit section of the
data bus. The data are held until the next OUT instruction executes. Thus, whenever the output
1 J> 3 4 5 6 7 8
U1 instruction is executed in this circuit, the data from the AL register appear on the LEDs.
1 2 1Y1 18
i! ———— 4
2A1 2Y1 Many I/O devices accept or release information at a much slower rate than the microprocessor.
7 10 ————ft 2A3 2Y3 5 Another method of I/O control, called handshaking or polling, synchronizes the I/O device with
8 9 17
2A4 2Y4 the microprocessor. An example device that requires handshaking is a parallel printer that prints
1G 100 characters per second (CPS). It is obvious that the microprocessor can send more than 100
2G CPS to the printer, so a way to slow the microprocessor down to match speeds with the printer
must be developed.
Figure 11-5 illustrates the typical input and output connections found on a printer. Here,
data are transferred through a series of data connections (D7-DO), BUSY indicates that the
printer is busy and STB is a clock pulse used to send data into the printer for printing.
The ASCII data to be printed by the printer are placed on D7-DO, and a pulse is then ap-
plied to the STB connection. The strobe signal sends or clocks the data into the printer so that it
Figure 11-4 shows how eight simple light-emitting diodes (LEDs) connect to the micro- can be printed. As soon as the printer receives the data, it places a logic 1 on the BUSY pin, in-
processor through a set of eight data latches. The latch stores the number output by the micro- dicating that the printer is busy printing data. The microprocessor software polls or tests the
processor from the data bus so that the LEDs can be lit with any 8-bit binary number. Latches are BUSY pin to decide whether the printer is busy. If the printer is busy, the microprocessor waits;
needed to hold the data because when the microprocessor executes an OUT instruction, the data if it is not busy, the microprocessor sends the next ASCII character to the printer. This process of
interrogating the printer is called handshaking or polling. Example 11-1 illustrates a simple
procedure that tests the printer BUSY flag and then sends data to the printer if it is not busy. The
FIGURE 11-4 The basic vcc PRINT procedure prints the ASCII-coded contents of BL only if the BUSY flag is a logic 0, in-
output interface connected to dicating that the printer is not busy. This procedure is called each time a character is to be
a set of LED displays. printed.
;A procedure that prints the ASCII contents of BL.
0000 PRINT PROC NEAR
. "* ^ ^ ^ ^ •^
•^ ^ "* "•* ^ ^ 0000 E4 4B IN AL,BUSY get BUSY flag
U1 0002 A8 04 TEST AL,BUSY_BIT test BUSY bit
0004 75 FA
0006 8A C3
if printer busy
get data from BL
8 D3 Q3 9 0008 E6 4A OUT PRINTER,AL send data to printer
13 D4 Q4 12 OOOA CB RET return from procedure
14 D5 Q5 15
18 D7 Q7 19 OOOB PRINT ENDP
Notes About Interfacing Circuitry
A certain part of interfacing requires some knowledge about electronics. This portion of the in-
troduction to interfacing examines some facts about electronic interfacing. Before a circuit or de-
vice can be interfaced to the microprocessor, the terminal characteristics of the microprocessor
and its associated interfacing components must be known, (This was introduced at the start of
SEL Chapter 10.)
11-1 INTRODUCTION TO I/O INTERFACE 391
CHAPTER 11 BASIC I/O INTERFACE
FIGURE 11-6 A single-
pole, single-throw switch in-
terfaced as a TTL device.
bounces, one of the two circuits depicted in Figure 11-7 can be constructed. The first circuit (a)
is a classical textbook bounce eliminator; the second (b) is a more practical version of the same
!2_ circuit. Because the first version costs more money to construct, in practice, the second would be
J4_ used because it requires no pull-up resistors and only two inverters instead of two NAND gates.
You may notice that both circuits in Figure 11-7 are asynchronous flip-flops. The circuit
of (b) functions in the following manner: Suppose that the switch is currently at position Q . If it
Connector CENT36 is moved toward Q but does not yet touch Q, the Q output of the circuit is a logic 0. The logic 0
state is remembered by the inverters. The output of inverter B connects to the input of inverter A.
Because the output of inverter B is a logic 0, the output of inverter A is a logic 1. The logic 1
output of inverter A maintains the logic 0 output of inverter B. The flip-flop remains in this state
until the moving switch-contact first touches the Q connection. As soon as the Q input from the
Connector DB25 switch becomes a logic 0, it changes the state of the flip-flop. If the contact bounces back away
from the Q input, the flip-flop remembers and no change occurs, thus eliminating any bounce.
DB25 CENT36 Pin number Pin number Function Output Devices. Output devices are far more diverse than input devices, but many are interfaced in
Pin number Pin number Function
12 Paper empty a uniform manner. Before any output device can be interfaced, we must understand what the volt-
Data Strobe 12
1 1 ages and currents are from the microprocessor or a TTL interface component. The voltages are TTL-
13 13 Select
2 2 Data 0 (DO) compatible from the microprocessor of the interfacing element. (Logic 0 = 0.0 V to 0.4 V; logic 1 =
14 14 Afd
3 Data 1 (Dl) 2.4 V to 5.0 V.) The currents for a microprocessor and many microprocessor-interfacing compo-
15 32 nents are less than for standard TTL components. (Logic 0 = 0.0 to 2.0 mA; logic 1 = 0.0 to 400 uA.)
4 4 Data 2 (D2)
16 RESET Once the output currents are known, we can now interface a device to one of the outputs.
5 5 Data 3 (D3)
31 Select in Figure 11-8 shows how to interface a simple LED to a microprocessor peripheral pin. Notice that
Data 4 (D4) 17
6 6 a transistor driver is used in Figure 1 l-8(a) and a TTL inverter is used in Figure 1 l-8(b). The TTL
18—25 19—30 Ground
7 7 Data 5 (D5) inverter (standard version) provides up to 16 mA of current at a logic 0 level, which is more than
17 Frame ground
8 Data 6 (D6) enough to drive a standard LED. A standard LED requires 10 mA of forward bias current to light. In
16 both circuits, we assume that the voltage drop across the LED is about 2.0 V. The data sheet for an
9 9 Data 7 (D7)
33 Ground LED states that the nominal drop is 1.65 V, but we know from experience that the drop is anywhere
10 between 1.5 V and 2.0 V. This means that the value of the current-limiting resistor is 3-° v/io mA or
Busy 300 Q. Since 300 Q is not a standard resistor value, we choose to use a 330 Q resistor.
FIGURE 11-5 The DB25 connector found on computers and the Centronics 36-pin connector In the circuit of Figure 1 l-8(a), we elected to use a switching transistor in place of the TTL
found on printers for the Centronics parallel printer interface. buffer. The 2N2222 is a good general-purpose switching transistor that has a minimum gain of
100. In this circuit, the collector current is 10 mA, so the base current will be 1/100 of the col-
lector current of 0.1 mA. To determine the value of the base current-limiting resistor, we use the
FIGURE 11-7 Debouncing VCC
switch contacts: (a) conven-
tional debouncing and
(b) practical debouncing.
392 CHAPTER 11 BASIC I/O INTERFACE 11-2 I/O PORT ADDRESS DECODING 393
FIGURE 11-8 Interfacing and A15-AO for isolated I/O. Sometimes, if the I/O devices use only fixed I/O addressing, we
an LED: (a) using a transistor decode only A7-AO. In the personal computer system, we always decode all 16 I/O port address
and (b) using an inverter. bits. Another difference is that we use the IORC and IOWC to activate I/O devices for a read or
330 write operation. On earlier versions of the microprocessor, IO/M = 1 and RD or WR are used to
activate I/O devices. On the newest versions of the microprocessor, the M/IO = 0 and W/R are
Input- Input used to activate I/O devices.
Decoding 8-Bit I/O Addresses
(a) (b) As mentioned, the fixed I/O instruction uses an 8-bit I/O port address that appears on A15-AO
as OOOOH-OOFFH. If a system will never contain more than 256 I/O devices, we often decode
only address connections A7-AO for an 8-bit I/O port address. Thus, we ignore address connec-
FIGURE 11-9 A DC motor 12V tion A15-A8. Embedded systems often use 8-bit port addresses. Please note that the DX register
interfaced to a system by can also address I/O ports OOH-FFH. If the address is decoded as an 8-bit address, we can never
using a Darlington-pair. include I/O devices that use a 16-bit I/O address.
Figure 11-10 illustrates a 74ALS138 decoder that decodes 8-bit I/O ports FOH through
F7H. (We assume that this system will only use I/O ports OOH-FFH for this decoder example.)
This decoder is identical to a memory address decoder except we only connect address bits
A7-AO to the inputs of the decoder. Figure 11-11 shows the PLD version, using a PAL for this
decoder. The PAL is a better decoder circuit because the number of integrated circuits has been
reduced to one device. The program for the PAL appears in Example 11-2.
0.1 mA current and a voltage drop of 1.7 V. The TTL input signal has a minimum value of 2.4 V
and the drop across the emitter-base junction is 0.7 V. The difference is 1.7 V, which is the EXAMPLE 11-2
voltage drop across the resistor. The value of the resistor is L7 v/o.i mA or 17K £1 Because 17K £1 AUTHOR Barry B. Brey
is not a standard value, we used an 18K £1 resistor. DATE 7/1/99
Suppose that we need to interface a 12 V DC motor to the microprocessor and the motor CHIP DECODERS PAL16L8
current is 1A. Obviously, we cannot use a TTL inverter for two reasons: the 12V signal would
burn out the inverter and the amount of current far exceeds the 16 mA maximum current from ;pins 1 2 3 4 5 6 7 8 9 1 0
AO Al A2 A3 A4 A5 A6 A7 NC GND
the inverter. We cannot use a 2N2222 transistor either, because the maximum amount of current
is 250 mA to 500 mA, depending on the package style. The solution is to use a Darlington-pair. ;pins 11 12 13 14 15 16 17 18 19 20
Figure 11-9 illustrates the motor connected to the Darlington-pair. The Darlington-pair NC F7 F6 F5 F4 F3 F2 Fl FO VCC
has a minimum current gain of 7000 and a maximum current of 4A. The value of the bias resistor EQUATIONS
is calculated like the one used in the LED driver. The current through the resistor is 1 A/7000, or
about 0.143 mA. The voltage drop across the resistor is 0.9 V because we have two diode drops /FO = A7 * A6 A5 * A4 * A3 /A2 * /Al * /AO
/Fl = A7 * A6 A5 * A4 * A3
instead of one. The value of the bias resistor is °-9 v/o.i43 mA or 6.29KQ. The standard value of /F2 = A7 * A6 A5 * A4 * A3
/A2 * /Al * AO
/A2 * Al * /AO
6.2 KQ is used in the circuit. The Darlington-pair must be heat-sinked because of the amount /F3 = A7 * A6 A5 * A4 * A3 /A2 * Al * AO
of current going through it and the diode must also be present to prevent the Darlington-pair /F4 = A7 * A6 * A5 * A4 * A3 * A2 * /Al * /AO
/F5 = A7 * A6 * A5 * A4 * A3 * A2 * /Al * AO
from being destroyed by the inductive kick-back from the motor. This circuit is also used to in- /F6 = A7 A6 A5 A4 A3 A2 * Al /AO
terface mechanical relays or just about any device that requires a large amount of current or a /F7 = A7 * A6 * A5 * A4 * A3 A2 Al AO
change in voltage.
FIGURE 11-10 A port de- Ul
coder that decodes 8-bit I/O
ports. This decoder generates Al 2 3 14 F1H
11-2 I/O PORT ADDRESS DECODING active low outputs for ports
A2 3 C Y2
Y3 ^12 F3H
I/O port address decoding is very similar to memory address decoding, especially for memory- A4 6 Gl p3 FTH
A3 4^ G2A Y5 Q p^r TT
mapped I/O devices. In fact, we do not discuss memory-mapped I/O decoding because it is Y6
treated the same as memory (except that the IORC and IOWC are not used because there is no IN r* G2B Y7
or OUT instruction). The decision to use memory-mapped I/O is often determined by the size of U2A 74ALS138
the memory system and the placement of the I/O devices in the system. A6
The main difference between memory decoding and isolated I/O decoding is the number of A7
address pins connected to the decoder. We decode A31-AO, A23-AO, or A19-AO for memory; 74LS10
394 CHAPTER 11 BASIC I/O INTERFACE 11-2 I/O PORT ADDRESS DECODING 395
FIGURE 11-11 APAL16L8 Ul 8-And 16-Bit I/O Ports
decoder that generates I/O AO 11 01 -19 FOH
12 02 -18 F1H Now that we understand that decoding the I/O port address is probably simpler than decoding a
port signals for port FOH-F7H. ^ X17 F2H
13 03 :i6 F3H memory address (because of the number of bits), we explain how data are transferred between
A4 15 O5 3H F4H the microprocessor and 8- or 16-bit I/O devices. Data transferred to an 8-bit I/O device exist in
A5 16 O6 X2~ F5H
A6 Oil F6H one of the I/O banks in a 16-bit microprocessor such as the 80386SX. The I/O system contains
17 O7 ^12 F7H
A7 18 08 two 8-bit memory banks, just as memory does. This is illustrated in Figure 11-13, which shows
19 the separate I/O banks for a 16-bit system such as the 80386SX.
Because two I/O banks exist, any 8-bit I/O write requires a separate write strobe to func-
16L8 tion correctly. I/O reads do not require separate read strobes. As with memory, the micro-
processor reads only the byte it expects and ignores the other byte. The only time that a read can
cause problems is when the I/O device responds incorrectly to a read operation. In the case of an
I/O device that responds to a read from the wrong bank, we may need to include separate read
Decoding 16-Bit I/O Addresses signals. This is discussed if the case arises later in this chapter.
We also decode 16-bit I/O addresses, especially in a personal computer system. The main differ- Figure 11-14 illustrates a system that contains two different 8-bit output devices, located at
ence between decoding an 8-bit I/O address and a 16-bit I/O address is that eight additional ad- 8-bit I/O address 40H and 41H. Because these are 8-bit devices and because they appear in dif-
dress lines (A15-A8) must be decoded. Figure 11-12 illustrates a circuit that contains a ferent I/O banks, we generate separate I/O write signals. Note that all I/O ports use 8-bit addresses.
PAL16L8 and an 8-input NAND gate used to decode I/O ports EFF8H-EFFFH. Thus, ports 40H and 41H can each be addressed as separate 8-bit ports, or together as one 16-bit
The NAND gate decodes the first eight bits of the I/O port address (A15-A8). The output port. The program for the PAL16L8 decoder used in Figure 11-14 is illustrated in Example 11—4.
of the NAND gate generates a signal to enable the PAL16L8 for any I/O address between EFOOH
and EFFFH. The PAL16L8 further decodes the I/O address to produce eight active low output
strobes EFF8H-EFFFH The program for the PAL16L8 decoder appears in Example 11-3. AUTHOR Barry B. Brey
DATE ' 7/3/99
EXAMPLE 11-3 CHIP DECODERA PAL16L8
AUTHOR Barry B. Brey
;pins 1 2 3 4 5 6 7 8 9 10
BHE IOWC AO Al A2 A3 A4 A5 A6 GND
CHIP DECODER9 PAL16L8
;pins 11 12 13 14 15 16 17 18 19 20
A7 NC NC NC NC NC NC 40 41 VCC
;pins 1 2 3 4 5 6 7 8 9 10
AO Al A2 A3 A4 A5 A6 A7 NAND GND EQUATIONS
;pins 11 12 13 14 15 16 17 18 19 20
NC EFFFH EFFEH EFFDH EFFCH EFFBH EFFAH EFF9H EFF8H VCC 740 = /BLE * /IOWC * /A7 * A6 * /A5 * /A4 * /A3 * /A2 * /Al
741 = /BHE * /IOWC * 7A7 * A6 * /A5 * /A4 * /A3 * /A2 * /Al
/A2 * /Al * /AO * /NAND
When selecting 16-bit wide I/O devices, the BLE (AO) and BHE pins have no function be-
/EFF8H = A7 A6 * A5 * A4 * A3 *
/EFF9H = A7 A6 * A5 * A4 * A3 * /A2 * /Al * AO * /NAND cause both I/O banks are selected together. Although 16-bit I/O devices are relatively rare, a few
/EFFAH = A7 A6 * A5 * A4 * A3 * /A2 * Al * /AO * /NAND
/EFFBH = A7 A6 * A5 * A4 * A3 * /A2 * Al * AO * /NAND
/EFFCH = A7 A6 * A5 * A4 * A3 * A2 * /Al * /AO * /NAND FIGURE 11-13 The I/O
A6 * A5 * A4 * A3 * A2 * /Al * AO * /NAND banks found in the 8086,
/EFFDH = A7
A6 * A5 * A4 * A3 * A2 * Al * /AO * /NAND BHE AO
/EFFEH = A7 80186, 80286, and 80386SX.
/EFFF7 = A7 A6 * A5 * A4 * A3 * A2 * Al * AO * /NAND FFFF FFFE
FIGURE 11-12 APAL16L8
decoder that decodes 16-bit A12_ Sx>^ AO
K~ 11 01 :>|f-|EE|
address EFF8H-EFFFH. 12 O2
74LS04 A2 —— | 13 O3 OTS— EFFA High bank Low bank
A3 —— i 14 04 OJf-EFFB
! U2 ___ 3_
& 15 O5
A15 2 A5 —— | 16 06
A6 —— 4- 17 O7
A13. ——— > o A7 —— | 18
y 19 O8 0005 0004
A11 5 110 0003
6 ^ 0002
A10 16L8 0001
A8. U -7/11 oon D15-
11-2 I/O PORT ADDRESS DECODING
396 CHAPTER 11 BASIC I/O INTERFACE 397
FIGURE 11-15 A 16-bit
FIGURE 11-14 An I/O port D15-D8
D15-D8 U2 I/O port decoded at I/O U2
decoder that selects ports
V-1- DO QO _1__ addresses 64H and 65H. VI8_ 1Y1 2
40H and 41H for output data. 1A1
__4_ Dl Ql _1_ Njfi_ 1A2 4
_z_ D2 Q2 _6__
J4_ 1Y3 1A3 6
D3 Q3 M2_ 1Y4 1A4 8
J1_ D4 Q4
12 Port41H V_9_ 2Y1 2A1 11 Port 65H
XJLL D5 Q5 J5_ 7 13
sai_ D6 Q6
J6_ VX. 2Y3 2A3 15
_18_ D7 Q7
19 V^_ 2Y4 2A4 17
———— lc OC 1G 3 1
11 >CLK 2G D 19
BHE __ L_ 11 -19 74ALS374 74ALS244
IOWC __ 2_ 12 02 ^18 Ul
AO __ 3_ ^17 IORC 1
13 O3 11 Ol -02 ——
Al __ i_ :>&-
14 04 12 02 :>1S_
A2 __ 5_ 15 05 o^- U3 13 03 ^~
A3 __ 6_
A4 __ 7_
A5 __ 8_
18 08 16 O6
A6 _ 9_ 19 / 0~
D2 Q2 -| —— A6 7
A7 11 110
Q7 nn ^ 14
ii >CLK OC 16L8
^ 7 13
2Y3 ?A3 15
D7-DO 2Y4 2A4
do exist for analog-to-digital and digit-to-analog converters, as well as for some video and disk
Figure 11-15 illustrates a 16-bit input device connected to function at 8-bit I/O addresses 32-Bit Wide I/O Ports
64H and 65H. Notice that the PAL16L8 decoder does not have a connection for address bit BLE
(AO) and BHE because these signals do not apply to 16-bit wide I/O devices. The program for Although 32-bit wide I/O ports are not common, they may eventually become commonplace be-
the PAL16L8, illustrated in Example 11-5, shows how the enable signals are generated for the cause of newer buses found in computer systems. The once-promising EISA system bus supports
three-state buffers (74ALS244) used as input devices. 32-bit I/O as well as the VESA local and current PCI bus, but these are found only in some com-
EXAMPLE 11-5 The circuit of Figure 11-16 illustrates a 32-bit input port for the 80386DX or 80486 mi-
croprocessor. As with prior interfaces, this circuit uses a single PAL to decode the I/O ports and
AUTHOR Barry B . Brey
four 74LS244 buffers to connect the I/O data to the data bus. The I/O ports decoded by this in-
DATE 7/5/99 terface are the 8-bit ports 70H-73H, as illustrated by the PAL program in Example 11-6. Again,
CHIP DECODERS PAL16L8 we only decode an 8-bit I/O port address.
;pins 1 2 3 4 5 6 7 8 9 10 EXAMPLE 11-6
IORC Al A2 A3 A4 A5 A6 A7 NC GND
;pins 11 12 13 14 15 16 17 18 19 20 AUTHOR Barry B. Brey
NC NC NC NC NC NC NC NC 06X VCC COMPANY BreyCo
EQUATIONS CHIP DECODERC PAL16L8
/064 = /IORC * /A7 * A6 * A5 * /A4 * /A3 * A2 * /Al 6 7 9 10