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Virtual Machine Support for Many-Core Architectures<br />Decoupling Abstract from Concrete Concurrency Models<br />Stefan ...
Agenda<br />Motivation<br />Concurrency Support for VM Instruction Sets<br />Methodology<br />Combining Different Models<b...
The Free Lunch Is Over<br />Many Core ≠ Many Core<br />Homogeneous vs. heterogeneous designs<br />Different memory and cac...
Abstract Concurrency Models<br />Broad range of programming models<br />Shared memory with locking is error-prone/hard<br ...
Virtual Machines as Abstraction Layer<br />3/21/09<br />5<br />1. Motivation<br />C#<br />Prolog, …<br />JVM/CLR/…<br />To...
Concurrency Support for VM Instruction Sets<br />3/21/09<br />6<br />
Methodology<br />To develop instruction set with concurrency support<br />Combination of concurrency models<br />Guideline...
Combining Different Models<br />3/21/09<br />8<br />2. Concurrency Support for VM Instruction Sets<br /><ul><li>Consider a...
Distil basic concepts/instructions
Analyze design space for ISA
Stepwise integration
Based on existing ideas</li></li></ul><li>Tradeoffs to be Considered<br />Model combinations<br />Different types/approach...
Research Platform<br />Requirements for an appropriate VM<br />Portable, support for Linux and MIPS<br />Available STM and...
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Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

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The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. We argue that today's virtual machines (VMs), which are a cornerstone of software development, do not provide sufficient abstraction for concurrency concepts. To overcome this shortcoming, we propose to integrate concurrency operations into VM instruction sets.

Since there will always be VMs optimized for special purposes, our goal is to develop a methodology to design instruction sets with concurrency support. Therefore, we also propose a list of tradeoffs that have to be investigated to advise the design of such instruction sets. As a first experiment, we implemented one instruction set extension for shared memory and one for non-shared memory concurrency. From our experimental results, we derived a list of requirements for a full-grown experimental environment for further research.

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Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

  1. 1. Virtual Machine Support for Many-Core Architectures<br />Decoupling Abstract from Concrete Concurrency Models<br />Stefan Marr<br />VrijeUniversiteitBrussel<br />PLACES Workshop, 22nd March 2009, York, UK<br />
  2. 2. Agenda<br />Motivation<br />Concurrency Support for VM Instruction Sets<br />Methodology<br />Combining Different Models<br />Investigate Tradeoffs<br />Research Platform<br />3/21/09<br />2<br />VM Support forMany-CoreArchitectures<br />
  3. 3. The Free Lunch Is Over<br />Many Core ≠ Many Core<br />Homogeneous vs. heterogeneous designs<br />Different memory and cache patterns/partitions<br />Different concrete concurrency models<br />3/21/09<br />3<br />1. Motivation<br />Cell Broadband Engine<br /> - 1 PPE, 8 SPE<br /> - bus interconnect<br />Intel Larrabee<br /> - up to 48 cores (IA32)<br /> - bus interconnect, virtual shared memory<br />Tilera TILE64 <br /> - 64 cores (MIPS)<br /> - up to 866 MHz<br /> - virtual shared memory<br />
  4. 4. Abstract Concurrency Models<br />Broad range of programming models<br />Shared memory with locking is error-prone/hard<br />STM and actors still not mainstream<br />Combinations and new approaches expected<br />3/21/09<br />4<br />1. Motivation<br />
  5. 5. Virtual Machines as Abstraction Layer<br />3/21/09<br />5<br />1. Motivation<br />C#<br />Prolog, …<br />JVM/CLR/…<br />Today, concurrency support is very limited!<br />
  6. 6. Concurrency Support for VM Instruction Sets<br />3/21/09<br />6<br />
  7. 7. Methodology<br />To develop instruction set with concurrency support<br />Combination of concurrency models<br />Guidelines for design decision, tradeoffs<br />Instruction set design <br />Application area<br />General purpose/multi-langVMs like JVM/CLR<br />Special purpose VMs like DalvikVM<br />3/21/09<br />7<br />
  8. 8. Combining Different Models<br />3/21/09<br />8<br />2. Concurrency Support for VM Instruction Sets<br /><ul><li>Consider abstract models separately
  9. 9. Distil basic concepts/instructions
  10. 10. Analyze design space for ISA
  11. 11. Stepwise integration
  12. 12. Based on existing ideas</li></li></ul><li>Tradeoffs to be Considered<br />Model combinations<br />Different types/approaches of integration<br />Instruction set size<br />Design space with respect to #instructions<br />Instruction set type<br />Opcode vs. higher level representation<br />…?<br />3/21/09<br />9<br />2. Concurrency Support for VM Instruction Sets<br />
  13. 13. Research Platform<br />Requirements for an appropriate VM<br />Portable, support for Linux and MIPS<br />Available STM and Actors languages/libraries<br />Unused instructions in bytecode/opcode set<br />Easy to adapt just-in-time compiler<br />3/21/09<br />10<br />
  14. 14. Tilera TILE64™<br />3/21/09<br />11<br />3. Research Platform<br /><ul><li>64 cores, up to 866 MHz
  15. 15. MIPS derived 32-bit VLIW ISA
  16. 16. L1 cache/core: 8KB instructions, 8KB data
  17. 17. L2 cache/core: 64KB
  18. 18. 4 DDR2 RAM controller</li></li></ul><li>Choosing a VM as Research Platform<br />3/21/09<br />12<br />3. Research Platform<br />
  19. 19. Discussion<br />3/21/09<br />13<br />VM Support forMany-CoreArchitectures<br />Methodology<br />Tradeoffs<br />Concurrency Model Integration<br />Research Platform<br />Instruction Set Design<br />

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