Downloaded 309 times
Uploaded byGichelle Amon
Harvard architecture
The Harvard architecture stores instructions and data in separate physical memory units. It originated from the Harvard Mark I computer which stored instructions on punched tape and data in electromechanical counters. In the Harvard architecture, the instruction and data memories can differ in width, timing, technology and addressing structures. Modern CPU designs often use a modified Harvard architecture, where the CPU contains separate instruction and data caches to enable high performance despite slower main memory access times.
More Related Content
Similar to Harvard architecture
Harvard architecture
- 1.
- 2. Harvard Architecture HARVARD ARCHITECTURE
- 3. Harvard Architecture A computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. HARVARD ARCHITECTURE
- 4. the IBMAutomatic Sequence Controlled Calculator (ASCC) -- also known as the Harvard Mark I -- the largest electromechanical calculator ever built and the first automatic digital calculator in the United States HARVARD ARCHITECTURE
- 5. Harvard Architecture There is no need to make the two memories share characteristics. In particular, the word width, timing, implementation technology, and memory address structure can differ. In some systems, instructions can be stored in read-only memory while data memory generally requires read-write memory. In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses. HARVARD ARCHITECTURE
- 6. Speed The speed of the CPU has grown many times in comparison to the access speed of the main memory. If, for instance, every instruction run in the CPU requires an access to memory, the computer gains nothing for increased CPU speed—a problem referred to as being "memory bound". It is possible to make extremely fast memory but this is only practical for small amounts of memory for cost, power and signal routing reasons. The solution is to provide a small amount of very fast memory known as a CPU cache which holds recently accessed data. HARVARD ARCHITECTURE
- 7. Internal vs. externaldesign Modern high performance CPU chip designs incorporate aspects of both Harvard and von Neumann architecture. In particular, the Modified Harvard architecture is very common. CPU cache memory is divided into an instruction cache and a data cache. Harvard architecture is used as the CPU accesses the cache. HARVARD ARCHITECTURE
- 8. Modern uses ofthe Harvard Architecture The principal advantage of the pure Harvard architecture—simultaneous access to more than one memory system—has been reduced by modified Harvard processors using modern CPU cache systems.
- 9. Digital signalprocessors Texas Instruments TMS320 C55x processors, as one example, have multiple parallel data buses (two write, three read) and one instruction bus. HARVARD ARCHITECTURE
- 10. Microcontrollers Examples include, theAVR by Atmel Corp, the PIC by Microchip Technology, Inc. and the ARM Cortex-M3 processor (not all ARM chips have Harvard architecture). AVR PIC Cortex-M3 processor HARVARD ARCHITECTURE
- 11. 1-3) FILL (1& 3 PWEDE MAGKABALIGTAD) #1 #2 #3 4) The IBM Automatic Sequence Controlled Calculator (ASCC) – also known as the _________. 5) TRUE/FALSE: CPU cache memory is divided into an instruction cache and a data cache. HARVARD ARCHITECTURE