Image scalar hw_algorithm

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Image scalar hw_algorithm

  1. 1. Image Scalar HW Algorithm By Sean Chen
  2. 2. <ul>Constrain </ul><ul><li>SOC Constrain </li><ul><li>External memory </li><ul><li>without bank or page support
  3. 3. One space </li><ul><li>( DATA = ARR[Address] ) </li></ul><li>One read/ write </li></ul><li>Communication Bus </li><ul><li>Burst Mode support
  4. 4. Interrupt
  5. 5. Arbiter
  6. 6. Master/Slaver </li></ul></ul></ul>Bus MEM IP
  7. 7. Analysis <ul><li>Constrain </li><ul><li>For loop extension </li><ul><li>I, j -> Address Mapped
  8. 8. Timing sequence </li></ul><li>I's it good ? </li><ul><li>No Burst type </li><ul><li>Not continuous Address </li></ul><li>Cycle time </li><ul><li>No reduce the computation time </li></ul></ul></ul></ul>R0 R1 R4 R5 W0 W0 W1 W2 C W2 W3 W4 W4 W5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
  9. 9. Issue case <ul><li>Issue case </li><ul><li>Communication </li><ul><li>Try to add Burst Mode </li><ul><li>Increase Utility rate
  10. 10. Easily into sleep/Idle mode
  11. 11. Decrease Bus access time </li></ul></ul><li>Computation </li><ul><li>PIPE line design </li><ul><li>PINPON Buffer </li></ul></ul><li>Cost function </li><ul><li>HW resource </li><ul><li>Area ( inside Buffer ) </li></ul></ul></ul></ul>
  12. 12. RD_BUF_0 RD_BUF_1 RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 WT_BUF_0 WT_BUF_1 Cycle 1 Cycle 2 0 1 2 3 4 5 6 7 0 1 2 3 2 3 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
  13. 13. RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 RD_BUF_1 WT_BUF_1 WT_BUF_0 RD_BUF_1 RD_BUF_0 Cycle 3 Cycle 4 4 5 6 7 0 1 2 3 2 2 3 3 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 4 5 6 7 4 4 5 5 2 2 3 3 4 4 5 5 2 2 3 3 4 5 6 7 4 5 6 7
  14. 14. RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 Cycle 5 RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 Cycle 6 8 9 10 11 4 5 6 7 4 4 5 5 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 2 3 3 2 2 3 4 8 9 10 11 4 5 6 7 4 4 5 5 6 6 7 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 2 3 3 4 4 5 5 0 0 1 1 2 2 3 3 2 2 3 3 4 4 5 5
  15. 15. Row Column Column detection Row detection Tn-1 Tn R1 R2 R2 D1 row R2 R2 D2 row R2 R2 D1 row R2 W1 D1,2 column S W1,2 W1 W1 R3 R2 R2 R2 W1 W1 W2,3 D2,3 column S S W2 D3 row R2 R2 R2 W1 W2.3 W3 S W BND 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 8 9 10 11 12 13 14 15
  16. 16. <ul>Performance estimation </ul><ul><li>Performance estimation </li><ul><li>Case 4x4 -> 8x8 direct transform </li><ul><li>One read/ write </li><ul><li>C >= R_Bus(16) + W_bus(64) + C(4)/PE(N) ; </li></ul></ul><li>Case 4x4 -> 8x8 Our case </li><ul><li>R_Buff dep 4, W_Buff dep 8
  17. 17. Burst Mode </li><ul><li>C >= ( 4*R_Bus(4) + 8*W_Bus(8) + S(6) ): </li></ul></ul></ul></ul>

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