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Integrating a custom AXI IP Core
in Vivado for Xilinx Zynq FPGA
based embedded systems
Vincent Claes
Overview
Vincent Claes
•Hardware connection Digilent Zybo board (Zynq
based)
•Custom IP Core
•Vivado Project
•C Applicatio...
Hardware connection
Vincent Claes
Vincent Claes
Hardware connection
Vincent Claes
VHDL Dice Controller Code
Vincent Claes
XDC (Xilinx Design Constraint File)
##Switches
set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[...
Create new Vivado project (first launch Vivado)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Create new Vivado project (HW)
Vincent Claes
Check the project settings
Vincent Claes
Check IP Settings in Project Settings
Vincent Claes
Check IP Settings in Project Settings
Vincent Claes
Custom IP Core (AXI + VHDL)
Vincent Claes
Vincent Claes
Create and Package IP
Vincent Claes
Create and Package IP
Vincent Claes
Create a new AXI4 peripheral
Vincent Claes
Peripheral details
Vincent Claes
Add Interfaces
Vincent Claes
Create Peripheral overview [Edit IP]
Vincent Claes
Add Sources (dice VHDL controller file)
Vincent Claes
Add Sources
Vincent Claes
Add or Create Design Sources
Vincent Claes
Add Source files
Vincent Claes
Add Sources
Vincent Claes
open dobbelsteen_v1_0_S00_AXI.vhd
Vincent Claes
Add the Dobbelsteen component in VHD file
Vincent Claes
Add User logic in VHD file
Vincent Claes
Add ports to top VHDL file of AXI IP
Vincent Claes
Add port to dobbelsteen_v1_s00_AXI
component
Vincent Claes
Port map in dobbelsteen top VHDL file
Vincent Claes
Package IP
Vincent Claes
Package IP – File Groups
Vincent Claes
File Groups (Extra – not in this project)
If you use IP from the Xilinx IP
Catalog don’t forget to Add
Sub-Core References...
File Groups (Extra – not in this project)
Vincent Claes
Package IP – Customization Parameters
Vincent Claes
Review and Package
Vincent Claes
Close AXI Custom IP Project
Vincent Claes
Check the project settings
Vincent Claes
Project Settings – Repository Manager
Vincent Claes
Create new project
Vincent Claes
Create Block Design
Vincent Claes
Vivado Project
Vincent Claes
Vincent Claes
Create Block Design
Vincent Claes
Add IP to Block Design
Vincent Claes
Select ZYNQ7 Processing System
Vincent Claes
Run Block Automation
Vincent Claes
Run Block Automation
Vincent Claes
Block Diagram is auto-updated
Vincent Claes
Add Dobbelsteen IP
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Add dobbelsteeen_v1.0 axi ip core
Vincent Claes
Run Connection Automation (AXI bus
connection)
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Run Connection Automation
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Block Design
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Make external
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Make external
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Create HDL Wrapper (top VHDL file)
Vincent Claes
Create HDL Wrapper
Vincent Claes
Add Sources (design constraints file)
Vincent Claes
Add Sources
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Add or Create Constraints
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Add Constraints file
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Add or Create constraints
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Generate Bitstream (HW)
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No Implementation Results Available
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Bitstream Generation Completed
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Export Hardware
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Export Hardware
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Launch SDK to start writing Software
Vincent Claes
C Application (SW on FPGA
platform)
Vincent Claes
Vincent Claes
Launch SDK
Vincent Claes
Hw platform overview
Vincent Claes
Start a new Application Project
Vincent Claes
Application Project
Vincent Claes
Create a Hello World C Application
Vincent Claes
Rewrite C Application
Vincent Claes
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Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedded systems

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VHDL Dice Controller Custom AXI IP Core

Published in: Engineering

Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedded systems

  1. 1. Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedded systems Vincent Claes
  2. 2. Overview Vincent Claes •Hardware connection Digilent Zybo board (Zynq based) •Custom IP Core •Vivado Project •C Application in SDK
  3. 3. Hardware connection Vincent Claes Vincent Claes
  4. 4. Hardware connection Vincent Claes
  5. 5. VHDL Dice Controller Code Vincent Claes
  6. 6. XDC (Xilinx Design Constraint File) ##Switches set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 ##Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 Vincent Claes
  7. 7. Create new Vivado project (first launch Vivado) Vincent Claes
  8. 8. Create new Vivado project (HW) Vincent Claes
  9. 9. Create new Vivado project (HW) Vincent Claes
  10. 10. Create new Vivado project (HW) Vincent Claes
  11. 11. Create new Vivado project (HW) Vincent Claes
  12. 12. Create new Vivado project (HW) Vincent Claes
  13. 13. Create new Vivado project (HW) Vincent Claes
  14. 14. Create new Vivado project (HW) Vincent Claes
  15. 15. Create new Vivado project (HW) Vincent Claes
  16. 16. Check the project settings Vincent Claes
  17. 17. Check IP Settings in Project Settings Vincent Claes
  18. 18. Check IP Settings in Project Settings Vincent Claes
  19. 19. Custom IP Core (AXI + VHDL) Vincent Claes Vincent Claes
  20. 20. Create and Package IP Vincent Claes
  21. 21. Create and Package IP Vincent Claes
  22. 22. Create a new AXI4 peripheral Vincent Claes
  23. 23. Peripheral details Vincent Claes
  24. 24. Add Interfaces Vincent Claes
  25. 25. Create Peripheral overview [Edit IP] Vincent Claes
  26. 26. Add Sources (dice VHDL controller file) Vincent Claes
  27. 27. Add Sources Vincent Claes
  28. 28. Add or Create Design Sources Vincent Claes
  29. 29. Add Source files Vincent Claes
  30. 30. Add Sources Vincent Claes
  31. 31. open dobbelsteen_v1_0_S00_AXI.vhd Vincent Claes
  32. 32. Add the Dobbelsteen component in VHD file Vincent Claes
  33. 33. Add User logic in VHD file Vincent Claes
  34. 34. Add ports to top VHDL file of AXI IP Vincent Claes
  35. 35. Add port to dobbelsteen_v1_s00_AXI component Vincent Claes
  36. 36. Port map in dobbelsteen top VHDL file Vincent Claes
  37. 37. Package IP Vincent Claes
  38. 38. Package IP – File Groups Vincent Claes
  39. 39. File Groups (Extra – not in this project) If you use IP from the Xilinx IP Catalog don’t forget to Add Sub-Core References in your File Groups!!! For instance when using the clock wizard inside your Custom VHDL IP block! Vincent Claes
  40. 40. File Groups (Extra – not in this project) Vincent Claes
  41. 41. Package IP – Customization Parameters Vincent Claes
  42. 42. Review and Package Vincent Claes
  43. 43. Close AXI Custom IP Project Vincent Claes
  44. 44. Check the project settings Vincent Claes
  45. 45. Project Settings – Repository Manager Vincent Claes
  46. 46. Create new project Vincent Claes
  47. 47. Create Block Design Vincent Claes
  48. 48. Vivado Project Vincent Claes Vincent Claes
  49. 49. Create Block Design Vincent Claes
  50. 50. Add IP to Block Design Vincent Claes
  51. 51. Select ZYNQ7 Processing System Vincent Claes
  52. 52. Run Block Automation Vincent Claes
  53. 53. Run Block Automation Vincent Claes
  54. 54. Block Diagram is auto-updated Vincent Claes
  55. 55. Add Dobbelsteen IP Vincent Claes
  56. 56. Add dobbelsteeen_v1.0 axi ip core Vincent Claes
  57. 57. Run Connection Automation (AXI bus connection) Vincent Claes
  58. 58. Run Connection Automation Vincent Claes
  59. 59. Block Design Vincent Claes
  60. 60. Make external Vincent Claes
  61. 61. Make external Vincent Claes
  62. 62. Create HDL Wrapper (top VHDL file) Vincent Claes
  63. 63. Create HDL Wrapper Vincent Claes
  64. 64. Add Sources (design constraints file) Vincent Claes
  65. 65. Add Sources Vincent Claes
  66. 66. Add or Create Constraints Vincent Claes
  67. 67. Add Constraints file Vincent Claes
  68. 68. Add or Create constraints Vincent Claes
  69. 69. Generate Bitstream (HW) Vincent Claes
  70. 70. No Implementation Results Available Vincent Claes
  71. 71. Bitstream Generation Completed Vincent Claes
  72. 72. Export Hardware Vincent Claes
  73. 73. Export Hardware Vincent Claes
  74. 74. Launch SDK to start writing Software Vincent Claes
  75. 75. C Application (SW on FPGA platform) Vincent Claes Vincent Claes
  76. 76. Launch SDK Vincent Claes
  77. 77. Hw platform overview Vincent Claes
  78. 78. Start a new Application Project Vincent Claes
  79. 79. Application Project Vincent Claes
  80. 80. Create a Hello World C Application Vincent Claes
  81. 81. Rewrite C Application Vincent Claes

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