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www.thalesgroup.com
Research & Technology
2012/07/17/Référence
www.flextiles.eu
Michael Hübner, ARC 2013
michael.huebner@r...
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Reconfigurable 3D MultiCore Concept by Prof. Michael Hübner @ ARC 2013

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The FlexTiles Project is developing tools and technology to enable design of Heterogeneous MulitCore solutions

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Reconfigurable 3D MultiCore Concept by Prof. Michael Hübner @ ARC 2013

  1. 1. www.thalesgroup.com Research & Technology 2012/07/17/Référence www.flextiles.eu Michael Hübner, ARC 2013 michael.huebner@rub.de Project coordinator: THALES Funding budget: 3,670,000€ Starting date: 15/10/2011 Duration: 36 months www.thalesgroup.com FlexTiles: Reconfigurable Multicore 3D Architecture
  2. 2. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Some Future applications within THALES Embedded Real-Time Market  low power consumption  low volumes  long life-time (~20 years) Adapt to environment  dynamicity, flexibility & dependability Smart cameraCognitive radio UAV More than static dataflow
  3. 3. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Manycore is a main issue for the industry  Programmability (industrial view):  Time to market  SW Development costs  Reuse of legacy code  What about Manycores?  Homogeneous?  Heterogeneous?
  4. 4. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Manycore is a main issue for the industry  Programmability (industrial view):  Time to market  SW Development costs  Reuse of legacy code  What about Manycores?  Homogeneous?  Heterogeneous? Why taking risks with Manycores ? We want to continue like in the good days: compile “without thinking” and get performances (keep it as long/simple as possible) !
  5. 5. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Homogeneous manycores: Good at Parallelism Parallelisation: raise computing power / lower power consumption. Homogeneity eases programming (C-Like + tools) but: Maximum performance only with static application. automatic optimisation (data parallelism) static allocation and scheduling. Else  Average performances / No guaranty Tilera - Tile-Gx100 – 100 cores  C/C++ Nvidia - Fermi - 512 cores  OpenCL/CUDA (C like+kernels) Kalray - MPPA - 256 cores  SigmaC (C++ like for dataflow)
  6. 6. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Customized/Customizable chips vs. FPGA Xilinx – ZYNQ : FPGA with a dual ARM A9 core  MPCore with reconfiguration capabilities ClusterCluster ClusterCluster ClusterCluster ClusterCluster ClusterCluster ClusterCluster ClusterCluster ClusterCluster ClusterCluster Fabric Controller core Fabric Controller core Fabric GOOD Parallelization POOR Customization POOR Parallelization GOOD Customization ST – P2012 (Heterogeneous manycore fabric)  Once done: Dedicated to a specific domain of applications  Affordable only for large series of products. Main issue: Domain dedication idem with MPSoCs (TI-OMAPs)
  7. 7. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence FlexTiles Proposes A 3D stacked chip based on:  A manycore layer  GPPs  DSPs  A FPGA layer  A 3D-NoC GOOD Parallelization GOOD Customization Customization at low price Opportunity: self adaptive capabilities  Future application needs
  8. 8. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Self adaptive?  Adapt the architecture to application requests at "real-time"  Improve yield and extend life-time of sub-micron technologies  Fault tolerance  Increase energy efficiency  give the right task to the best available processor  finalize the mapping at runtime  Temperature management  re-mapping How to program it?
  9. 9. // TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Holistic Approach: Model of Execution Model of ComputationModel of Computation Optimisation toolsOptimisation tools Programming Efficiency Self-Adaptive Capabilities Relocation strategiesRelocation strategies Model of programmationModel of programmation Flexible HardwareFlexible Hardware Common InterfacesCommon Interfaces Model of Execution
  10. 10. 0 /0 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Model of Execution Master NodesMaster Nodes Slave NodesSlave Nodes GPP nodes eFPGA nodes DSP nodes GPP Node accelerator node NI NoC NI Accelerator Interface (AI) acc requests control / status control / status DMA DMA requests data Master-slave execution model AI HW / SW independency regarding accelerator specificities
  11. 11. 5 /5 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Programming efficiency: Model of Computation Programming Efficiency Self-Adaptive Capabilities Relocation strategiesRelocation strategies Model of programmationModel of programmation Flexible HardwareFlexible Hardware Common InterfacesCommon Interfaces Model of ExecutionModel of Execution Optimisation tools Model of ComputationModel of Computation
  12. 12. 6 /6 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Applicatio n (C code) Applicatio n (C code) C to SpearDE representation Conversion (Cosy) C to SpearDE representation Conversion (Cosy) Data parallelisation Mapping (SpearDE) Data parallelisation Mapping (SpearDE) Graphic input (manual) + C kernels Graphic input (manual) + C kernels Streaming optimisation (Cosy) Streaming optimisation (Cosy) Compilation & Link (Cosy) Compilation & Link (Cosy) architecture representation architecture representation Master coresMaster coresSlave coresSlave cores Library of IPsLibrary of IPs Tool flow and MoC Tool flow based : Thales - SpearDE ACE - Cosy Programming efficiency: Model of Computation Binaries Acc compiler or C2VHDL toolsAcc compiler or C2VHDL tools
  13. 13. 7 /7 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Programming efficiency: Model of Computation Programming Efficiency Self-Adaptive Capabilities Relocation strategiesRelocation strategies Model of programmationModel of programmation Flexible HardwareFlexible Hardware Model of ExecutionModel of ExecutionModel of ComputationModel of Computation Common Interfaces Optimisation toolsOptimisation tools
  14. 14. 8 /8 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Modularity and scalability: common interfaces Homogeneous GPP nodes Heterogeneous accelerators nodes GPP Node AI DSP Node NI GPP Node NI NoC NI NI NI AI AI NI Config. Ctrl. DDR Ctrl. NI GPP Node NI I/O NI Generic Interfaces eFPGA Domain (Reconfigurable HW acc.) Dedicated Accelerator Node Dedicated Accelerator Node
  15. 15. 9 /9 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Relocation Strategies Programming Efficiency Self-Adaptive Capabilities Model of programmationModel of programmation Flexible HardwareFlexible Hardware Model of ExecutionModel of ExecutionModel of ComputationModel of Computation Optimisation toolsOptimisation tools Relocation Strategies Common InterfacesCommon Interfaces
  16. 16. 0 /0 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence A1.1A1.1 A2.1A2.1 A3A3 A5A5 A4A4 A1.2A1.2 A2.2A2.2 A1.3A1.3 A2.3A2.3 A1.4A1.4 A2.4A2.4 •FPGA•FPGA •GPP•GPP •FPGA•FPGA A1.1A1.1 A2.1A2.1 A3A3 A5A5 A4A4 A1.2A1.2 A2.2A2.2 A1.3A1.3 A2.3A2.3 A1.4A1.4 A2.4A2.4 •DSP•DSP •GPP•GPP •DSP•DSP A1.1A1.1 A2.1A2.1 A3A3 A5A5 A4A4 A1.2A1.2 A2.2A2.2 A1.3A1.3 A2.3A2.3 A1.4A1.4 A2.4A2.4 •DSP•DSP •DSP•DSP •DSP•DSP timerelocation relocation relocation Relocation Strategies
  17. 17. 1 /1 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Self-adaptation Accelerator/Virtual Code Dynamic allocation / binding DIAGNOSI S O = F(L) ACTION SYSTEM MONITORING GPP Node AI DSP Node NI GPP Node NI NoC NI NI NI AI AI NI Config. Ctrl. DDR Ctrl. NI GPP Node NI I/O NI Dedicated Accelerator Node Dedicated Accelerator Node eFPGA Domain (Reconfigurable HW acc.)
  18. 18. 2 /2 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Flexible Hardware Programming Efficiency Self-Adaptive Capabilities Model of programmationModel of programmation Model of ExecutionModel of ExecutionModel of ComputationModel of Computation Optimisation toolsOptimisation tools Common InterfacesCommon Interfaces Flexible Hardware Relocation strategiesRelocation strategies
  19. 19. 3 /3 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Tile Tile Tile Tile Tile Tile Tile Tile Tile New dynamic reconfigurable technology Homogeneous manycore NoC FlexTiles: a 3D stack chip 3D stacked reconfigurable layer
  20. 20. 4 /4 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Tile Tile Tile Tile Tile Tile Tile Tile Tile New dynamic reconfigurable technology 3D stacked reconfigurable layer Homogeneous manycore NoC FlexTiles: a 3D stack chip Map Accelerated functions
  21. 21. 5 /5 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Tile Tile Tile Tile Tile Tile Tile Tile Tile New dynamic reconfigurable technology 3D stacked reconfigurable layer Homogeneous manycore NoC FlexTiles: a 3D stack chip Duplicate
  22. 22. 6 /6 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Tile Tile Tile Tile Tile Tile Tile Tile Tile New dynamic reconfigurable technology 3D stacked reconfigurable layer Homogeneous manycore NoC FlexTiles: a 3D stack chip Migrate
  23. 23. 7 /7 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Holistic Approach Model of programmationModel of programmation Model of ComputationModel of Computation Model of ExecutionModel of Execution Flexible HardwareFlexible Hardware Common InterfacesCommon Interfaces strategies of relocationstrategies of relocation Optimisation toolsOptimisation tools
  24. 24. 8 /8 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence NoC QoS chipchip GPP icache dcache dLMEM GPP NI iLMEM eFPGA eFPGA dLMEM eFPGA iLMEM DSP DSP dLMEM DSP DDR NI + DDR ctrl on chip shMEM NI NI control NOC bitstream NOC data NOC instruction NOC test/debug NOC
  25. 25. 9 /9 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence ANoC (CEA) GALS: asynchronous logic in nodes, local synchronous cores -highly scalable -between nodes: no global clock, not even local clock -power efficient and dependable -packet switching -wormhole protocol -low latency
  26. 26. 0 /0 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence AEtheral NoC (TUe) Guaranteed levels of services and performances Contention free routing by construction - wormhole routing specified at design time Globally Synchronous with time slots
  27. 27. 1 /1 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Conclusion Parallelisation is the only way to reach HPC for low power consumption. But parallelisation is not enough, customisation is also necessary  Only affordable for high volumes Reconfigurable customisation is the solution:  Increase accessibility to heterogeneous manycore technology  Offers self-adaptive capabilities
  28. 28. 2 /2 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Our proposition: a 3D stacked chip and … A 3D stacked chip based on:  A manycore layer  GPPs  DSPs  A FPGA layer  A 3D-NoC
  29. 29. 3 /3 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence …a complete platform Virtualisation layer Virtualisation layer relocatable binary coderelocatable binary code Parallelisation, partioningParallelisation, partioning Application Hardware Nodes CompilationCompilation Synthesis, P&RSynthesis, P&R relocatable bitstreamrelocatable bitstream Hardware Abstraction Layer Hardware Abstraction Layer API Operating Library API KernelKernel Resource Monitoring & Allocation Resource Monitoring & Allocation DIAGNOSIS O = F(L) ACTION SYSTEM toolchain operating library heterogenous manycore MONITORING
  30. 30. 4 /4 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence Consortium and questions Partners & Third Party Country Main scientific and technical contributions THALES France Infrastructure and applications KIT Germany Virtualisation layer TUE Netherlands Kernel ; NoC CSEM Switzerland DSP CEA France NoC ; 3D stacking UR1 France Reconfigurable technology SUNDANCE United Kingdom FPGA Demonstrator ACE Netherlands Parallelisation and compilation Tools RUB Germany Reconfigurable technology 8 partners in 5 countries
  31. 31. 5 /5 / TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofTHALES.Youareherebynotifiedthatanyreview,dissemination,distribution,copyingor otherwiseuseofthisdocumentisstrictlyprohibitedwithoutThalespriorwrittenapproval.©THALES2011.Templatetrtpversion7.0.8 Date/Référence FlexTiles With FlexTiles, The Industry will be able to… take the plunge into the manycore world!

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