SFBC (labeled as +1) that controls the amount of positive-
sequence fundamental current in phase with the grid voltage.
On the other hand, in order to balance VDC1 and VDC2 , i∗ (in
iN fact io ) is drained from the middle point of the capacitors. For
POWER GRID example if the difference between VDC1 and VDC2 (relative
to VDC ) increases, the control drains a current i∗ that tends
(one per phase)
to increase VDC2 and reduce VDC1 .
In the next subsection, a simple small-signal model for the
C dynamics of the DC voltages is derived. It is shown that this
+ control strategy creates two decoupled loops. The model is
SHUNT ACTIVE - also shown to be useful for optimizing the performance of the
FILTER in control loop.
VSI: VOLTAGE SOURCE INVERTER
B. Analysis of the Control Loop
Fig. 3. Four wire VSI with split DC bus. The dynamics of the capacitor voltages are usually much
slower than the dynamics of the VSI currents. Under this
assumption, the VSI can be represented as a static mapping
VDC from the reference currents to the actual currents. As shown in
Fig. 5 the VSI references are the desired ﬁlter currents iF α ,
VDC ¡ p* iF β and i∗ , which the inverter is going to follow with an
internal current control method that is of no interest in this
+ derivation. Without loss of generality, the p-q transformation
VDC ¢ io* can be lumped into the VSI and therefore it can be assumed
- that the VSI references are actually pF , qF and i∗ . On oF
the other hand, the actual currents on the VSI will affect
Fig. 4. VDC and balance control strategy. the capacitor voltages. The outputs of interest for feedback
purposes are VDC1 +VDC2 and VDC1 +VDC2 as shown in Fig. 4.
In spite of its complexity, the ﬁltering mechanisms in Fig. 5
II. C ONTROL OF THE DC VOLTAGES are actually of no relevance to the DC voltage control loop. In
A. Control Strategy fact, they are located in the feedforward path so the reference
signals they generate can be considered external perturbations
The four-wire VSI used is shown in Fig. 3. In order to
with no effect on the performance and stability of the feedback
control the total voltage VDC = VDC1 + VDC2 and to
loop. To clarify this concept, the control loop is redrawn as in
balance voltages VDC1 and VDC2 , a new decoupled strategy
was proposed in . The controller is shown in Fig. 4. The
For the purpose of analyzing the feedback loop it is neces-
compensation signals p∗ and io ∗ are utilized as shown in
sary to derive the mappings from the commanded active power
and the commanded homopolar current to the VSI currents on
This control strategy is based on physical concepts. In order
the DC side. Then, those currents are applied to the capacitors
to control VDC , active power (in fact instantaneous active
to derive the output voltages as illustrated in Fig. 7. The total
power p) is subtracted or added to the busbar. This is achieved
active power at the VSI DC-side can be computed as
by injecting the p∗ control signal in the p channel of the last
p∗ = iC1 vC1 + iC2 vC2 .
iL p* iC The neutral current is
in = iC1 − iC2 (5)
iFβ 1 β
iβ -1 n2 n1 / where in = 3io (Clarke transformation).
qF* q From (4) and (5), the capacitor currents are
p∗ + in vC2
+ iC1 =
vC1 + vC2
io* - Multiple bandpass filter
p∗ − in vC1
iC2 = . (6)
vC1 + vC2
Fig. 5. Complete four-wire selective ﬁltering control strategy including
control of the DC voltages. This implies that the dynamics of the capacitor voltages are
pF qF ioF
the load homopolar current is measured, then the transformer
p∗ ratio must be considered.
− VDC1 + VDC2 The outputs are deﬁned as y1 = x1 and y2 = x2 . The
small-signal relationship is then
VSI y1 1 0 x1
= 0 1 . (10)
VDC1 +VDC2 y2 VDCref x2
∆VDC = 0 K2 o
From (9) and (10) the two-input two-output transfer function
VDCref C s+ RC 0
H(s) = √ . (11)
VDCref C s+ RC
Fig. 6. DC voltages control loop.
It is then conﬁrmed that this control strategy actually decou-
iC1 ples the two loops and the controller design reduces to two
standard single-input single-output (SISO) loops with a ﬁrst-
+ order plant on each.
vC1 C R
in III. S IMULATIONS AND E XPERIMENTAL R ESULTS
In this section simulated results made with Simulink and an
experimental validation of the implementation of the control
vC2 C R
in the DSP TM320F2812 (kit F2812 eZdsp) are shown. The
− VSI current control is hysteretic at a regular sampling period.
Data: VDCref = 340V , C = 4400µF , grid voltage
iC2 U = 380V , grid frequency f = 50Hz, L = 10mH. The
Fig. 7. Simpliﬁed model of the VSI DC-side.
transformer indicated in Fig. 3 has a ratio of 220 : 55 = 4.
The sample and control frequency was fm = 20kHz (400
samples for each grid cycle) so Tm = 50µs. The time delay
given by introduced by the DSP depends on the number of harmonic
sequences being ﬁltered, and is equal to 16.2µs plus 2.8µs
dvC1 vC1 per homopolar sequence and 3.2µs per positive or negative
C = iC1 −
dt R sequence.
p∗ + in vC2
= − Having in mind the commutation losses, this sampling and
vC1 + vC2 R control frequency is equivalent to a fm = 20kHz/2 = 10kHz
dvC2 vC2 averaging P W M current control.
C = iC2 −
dt R Figure 8 shows the selective ﬁlter operation for a dim-
p∗ − in vC1
F vC2 merized resistive load. The line current is shown before and
= − . (7)
vC1 + vC2 R after applying the ﬁlter. Three different conﬁgurations of the
Let x1 = vC1 + vC2 and x2 = vC1 − vC2 , then selective ﬁlter are shown: ﬁltering all harmonics (up to the
dx1 2p∗ − in x2 x1 17th), ﬁltering only 5th and 7th harmonics, and ﬁltering only
C= − the homopolar multiples-of-3 harmonics. No passive ﬁlters
dt x1 R
were used in this experiment.
C = in − (8) The small-signal model (11) is validated with a simulation
of the DC voltage response to a step in the reference voltage.
The equations are nonlinear, so a small-signal model will The PI controllers were tuned to achieve a bandwidth of 10Hz
be derived by linearization. The operation point (noted with and a phase margin of 45◦ , using standard techniques based on
capital letters) is given by X1 = VDCref , X2 = 0, PF = the small-signal model. The bandwidth was selected such that
2R , and In = 0. Then the small-signal model is the voltage regulation loops do not interfere with the proper
2 functioning of the ﬁlter; a justiﬁcation for this is included in
d x1 − RC 0 x1
= 1 + the appendix.
dt x2 0 − RC x2 The output of the small-signal model is compared to that of
VDCref C 0 p∗
a full switched model and experimental results in Fig. 9. The
0 3 i∗
correlation between the models and the experimental results
√ is very good.
where the relationship in = 3i∗ was used. Here, i∗ is the
o o Figure 10 shows the responses of both the total voltage
homopolar current at the inverter side of the transformer. If VDC1 + VDC2 and the difference VDC1 − VDC2 to a step in
Fig. 8. Load current and selective ﬁltering. Left: voltage and current waveforms; right: line current spectrum. (a) Load current without ﬁltering. (b) Filtering
all harmonics up to the 17th. (c) Filtering 5th and 7th harmonics. (d) Filtering homopolar multiple-of-3 harmonics.
Response to a step in V Response to a step in ∆ V
354 350 350
348 330 330
−0.5 0 0.5 1 −0.5 0 0.5 1
342 10 10
averaged simulation 0 0
0 0.05 0.1 0.15 0.2 0.25 0.3 −10 −10
t (s) −0.5 0 0.5 1 −0.5 0 0.5 1
Fig. 9. Step response of the total voltage VDC1 + VDC2 to a change in the Fig. 10. Step response of the two voltage loops. This experiment shows the
reference value. The small-signal model is compared with a switching model decoupling as predicted by the model.
and experimental results.
the reference for each loop. The decoupling between the two
becomes very clear, in agreement with the model (11). ∞
In Figs. 9 and 10, the experimental voltage shown was p(t)
¯ = 3V+n I+n cos(φ+n − δ+n ) +
acquired with the DSP that introduces noise due to the signal n=1
3V−n I−n cos(φ−n − δ−n ) (17)
IV. C ONCLUSIONS n=1
This paper presents a controller for the DC voltages on
the split capacitor topology for a four-wire selective active p(t) =
ﬁlter. The main contribution of the paper is the derivation of
a small-signal model for the dynamics of the DC voltages in 3V+m I+n cos[(wm − wn )t + φ+m − δ+n ]
the two capacitors. This model enables the deﬁnition of the m=n
controller parameters using standard techniques for LTI SISO ∞ ∞
systems. The beneﬁts of this approach are illustrated with + 3V−m I−n cos[(wm − wn )t + φ−m − δ−n ]
simulations and experimental results. Further, the appendix m=1
presents a theoretical justiﬁcation for selecting the bandwidth ∞ ∞
of the voltage control loops, also illustrated with experimental − 3V+m I−n cos[(wm + wn )t + φ+m + δ−n ]
results. m=1 n=1
A PPENDIX − 3V−m I+n cos[(wm + wn )t + φ−m + δ+n ]
This appendix shows that, under normal operation, the m=1 n=1
voltage at the capacitors have a ripple which has a frequency where wk = kw is the k-th harmonic frequency, V+k ,
that depends on the current harmonic sequences being ﬁltered. V−k and V0k are the amplitudes of the positive, negative
The results included in this appendix are useful to deﬁne the and homopolar k-th harmonic sequences respectively (same
bandwidth of the voltage control loops such that they do not notation for currents), and φ∗ and δ∗ are the angles for the
interfere with the normal ﬁlter operation. corresponding harmonic sequence component for voltages and
First, harmonic expressions for power and homopolar cur- currents respectively.
rent are derived. Next, the effect of the oscillatory part of these Finally, the homopolar current is expressed in terms of the
expressions on the capacitor voltages is derived. corresponding homopolar sequences:
The three-phase power in a four-wire system is
p3 = p0 + p (12) √
i0 (t) = 6I0n sin(wn t + δ0n ) (19)
where p is the instantaneous power as deﬁned in the p − q
transformation, and p0 is the instantaneous homopolar power. A. Homopolar sequence
In steady-state, the instantaneous values p0 and p have In case of using the inverter to ﬁlter a unique homopolar
average values of p0 and p respectively. Then, the oscillatory
¯ ¯ sequence of index n, from (19) the current can be expressed
values p0 and p are deﬁned such that
˜ ˜ as √
i0 (t) = 6I0n sin(wn t + δ0n ) (20)
p0 = p0 + p0
¯ ˜ (13)
p = p+p
¯ ˜ (14) Since there are no positive nor negative current harmonic
sequences, from (17) and (18) p is zero which implies p3 = p0 .
Expressions for p0 , p0 , p and p as a function of the harmonic
¯ ˜ ¯ ˜ Then, from (15) and (16) p3 is
sequences (positive, negative and homopolar) of voltage and
current in the three-phase system were presented in ,  p3(t) = 3V0n I0n cos(φ0n − δ0n )
and reproduced here: − 3V0n I0n cos[(wn + wn )t + φ0n + δ0n ] (21)
∞ Assuming the inverter has only an inductive load (decou-
p0 (t) =
¯ +3V0n I0n cos(φ0n − δ0n ) (15) pling impedance between the inverter and an ideal electric
n=1 network) and setting arbitrarily δ0n = 0, then φ0n = π/2. The
ﬁnal expressions for the homopolar current and the power are
p0 (t) =
˜ (16) √
∞ ∞ i0 (t) = 6I0n sin(wn t) (22)
3V0m I0n cos[(wm − wn )t + φ0m − δ0n ] p3(t) = −3V0n I0n cos[(2wn t) + π/2] (23)
∞ ∞ For example, if n = 3 (ﬁltering the third harmonic of the
− 3V0m I0n cos[(wm + wn )t + φ0m + δ0n ] homopolar) then i0 has a 3rd harmonic and p3 a 6th harmonic.
m=1 n=1 When these inputs excite the system described by (8), the
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Fig. 12. Voltage ripple generated by ﬁltering the positive 3rd harmonic
Fig. 11. Voltage ripple generated by ﬁltering the homopolar 3rd harmonic sequence on VDC1 + VDC2 .
C APACITOR VOLTAGE R IPPLE F REQUENCY
resulting voltages vC1 and vC2 have a dominant ripple with
0n +n −n
a 3rd harmonic with opposite phases, and the 6th harmonic
vC1 + vC2 2n n−1 n+1
appears in the total voltage vC1 + vC2 due to the cancellation
vC1 , vC2 n n−1 n+1
of the 3rd harmonic between vC1 and vC2 . This is illustrated vC1 − vC2 n – –
by the experimental results shown in Fig. 11.
B. Positive/negative sequence
This result implies that the ripple at the capacitor voltages
In this case the homopolar current is null, so i0 (t) = 0.
has the same frequency as that of p3, namely w1 ∓ wn . In
As in the previous section, the impedance seen by the
Fig. 12 experimental results are shown when ﬁltering the +3
harmonic sequences is a pure inductance, for a given I±n
harmonic sequence; as expected, a ripple at 100Hz appears at
there will be a corresponding V±n . Then,
the DC bus voltage.
p(t) = +3V±n I±n cos(φ±n − δ±n )
C. Combination of Sequences
Setting arbitrarily δ±n = 0, then φ±n = π/2 which results in Although the system is non-linear, it was shown that
p(t) = 0.
¯ to a ﬁrst-order approximation the dynamics are decoupled.
Since the three-phase system is ideal, there is only V+1 , so Therefore, superposition can be applied to a certain extent.
from (18) It is concluded that the harmonic components present in the
p(t) = p3(t) = ±3V+1 I±n cos[(w1 ∓wn )t+φ+1 ∓δ±n ] (25)
˜ capacitor voltage ripples will be given by the results of the
previous analysis, summarized in Table I.
For example, if the harmonic sequence −3 is ﬁltered, then These results are illustrated with the experimental wave-
p3 will have a frequency component at w1 + w3 = w4 which forms shown in Fig. 13, in which both the homopolar 3rd
implies an oscillation at 4 × 50Hz = 200Hz. Similarly, if the
sequence +3 is ﬁltered, the oscillation at p3 will happen at
Since i0 = 0, the solution to (8) is simpler than in the
previous case and can be computed analytically. Clearly the
difference between the voltage on the capacitors is zero so −0.5
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
vC 1(t) = vC 2(t) = vc2 . Let pM be the amplitude of p3 as 0.5
given in (25), and let arbitrarily choose φ+1 ∓ δ±n = 0. Then
the result is
pM = ±3V+1 I±n (26) 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
e(0) = vc (0)2 (27)
4 pM −0.5
vc (t) = sin(w1 ∓ wn )t + e(0) (28) 0 0.002 0.004 0.006 0.008 0.01
0.012 0.014 0.016 0.018 0.02
where vC (0) is the initial value for the total voltage on the Fig. 13. Voltage ripple generated by ﬁltering the homopolar 3rd and the −5
DC bus. harmonic sequences simultaneously.
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