Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Slides cmsb13

394 views

Published on

Published in: Technology, Education
  • Be the first to comment

  • Be the first to like this

Slides cmsb13

  1. 1. A temporal logic approach to modular design of synthetic biological circuits Ezio Bartocci1, Luca Bortolussi2 and Laura Nenzi3 1Vienna University of Technology, Austria 2DMG, University of Trieste, Italy and CNR/ISTI, Pisa, Italy 3IMT Lucca, Italy CMSB 2013, IST Austria, Klosterneuburg, Austria
  2. 2. Outline • Motivation • Synthetic biological circuits, overview of our approach • Background • Signal Temporal Logic, gene regulatory networks • Logical characterization of modules • Module specification, AND gate example, network of modules, constraints for acyclic networks • Parameter Synthesis • Worst case analysis, parameter synthesis algorithm, Half- adder case study • Conclusion and Future Work
  3. 3. Motivation
  4. 4. Synthetic Biological Circuits (1) Biological parts inside a cell are designed to perform logical functions mimicking those observed in electronic networks. Examples: AND Signal A Signal B Signal O Activating Promoter SignalA Activating Promoter SignalB Gene1 Product (protein) Gene1 Product (protein) Gene 1 Gene 2 Controlled Gene Activating Promoter Desired Gene Product OR Signal A Signal B Signal O Activating Promoter SignalA Activating Promoter SignalB Gene1 Product (protein) Gene1 Product (protein) Gene 1 Gene 2 Activating Promoter Desired Gene Product Activating Promoter Controlled Gene NAND Signal A Signal B Signal O Activating PromoterSignalA Activating Promoter SignalB Gene1 Product (protein) Gene1 Product (protein) Gene 1 Gene 2 Contr. Gene Repressing Promoter Desired Gene Product
  5. 5. Synthetic Biological Circuits (2) Biological circuits are complex systems psicA sicA* invF rfp pipaH* mxiE ipgC pexsC exsC exsDA pTet* tetR luxR pLux* pTac pBADaraC lacl [Ara] [IPTG] [3OC6] [aTc] Genetic programs constructed from layered logic gates in single cells Tae Seok Moon et al., Nature 491, 249–253, 2012 A possible approach: taming the complexity through modularity We divide the system in subunits (modules) and look a we study the interactions between them. Typically the behavior of each module is formally specified in terms of a truth table [Ara] [IPTG] [pipaH*] High High High High Low Low Low High Low Low Low Low Drawback: this specification does not consider time properties: delays and synchronization among modules
  6. 6. Related Work • The majority of existing approaches relies on brute-force techniques running sophisticated optimization algorithms (i.e. evolutionary algorithms, simulating annealing, etc.) to tune the kinetic parameters, lacking of compositionality • A more rational approach was recently proposed by Marchisio and Stelling (ACS Synth Biol 2012, PloS Comp. Biol 2011), where they proposed a workflow taking a target truth table as input and generating several possible circuit schemes. • Signal compatibility among modules is taken in consideration in Yaman et al. ACS Synth Biol 2012 • Batt et. al approximate the behavior of genetic networks with piecewise multi-affine systems. The state-space is partitioned in hyper-rectangles exhibiting useful convexity properties that allows to compute an over-approximation of the reachable sets.
  7. 7. Overview of our approach A B S C Network of acyclic tunable modules of the target circuit Temporal Logic Specification of tunable modules Temporal Logic Specification of the target circuit A B S C Target circuit specification Target Circuit A B S C Final Design robust parameter range search for each module robust parameter range search for the network  0,l+d[ ] xA ³qA+ Ù xB ³qB+( )® à 0,d[ ] 0,l[ ] xC ³qC+( ) jINPUT ®jOUTPUT
  8. 8. Background
  9. 9. Signal Temporal Logic (1) Linear Temporal Logic (LTL) Time point-based semantics Boolean Variables A. Pnueli, 1977 Families of Temporal Logics Metric Interval Temporal Logic (LTL) Interval-based dense time semantics Boolean Signals R. Alur, T. Feder, T. A. Henzinger, 1991 Signal Temporal Logic (STL) Interval-based dense time semantics Real-valued signals O. Maler, D. , Nickovic, 2004 STL Syntax The Signal Temporal Logic (STL) is a temporal logic, suitable to characterize behavioral patterns in time series of real values generated during the simulation of a dynamical system. Given a signal x t[ ]= x1 t[ ], ,xn t[ ]( ),t Î ³0,xi Î , the STL syntax is given by: j := m | Øj | j1 Ù j2 | j1 U a,b[ ] j2 where m :  n ® 0,1{ } is an atomic predicate s.t. m x( ):= y x( ) ³ 0( ), with y :  n ®  a real-valued function. Furthermore, à a,b[ ]j := T U a,b[ ] j and  a,b[ ]j := Øà a,b[ ]Øj
  10. 10. Signal Temporal Logic (2) STL Quantitative Semantics (space robustness) The quantitative satisfaction function r satisfies the following: r m,x,t( ) = y x t[ ]( ) where m º y x[t]( ) ³ 0( ) r Øj,x,t( ) = -r j,x,t( ) r j1 Ùj2,x,t( ) = min r j1,x,t( ),r j2,x,t( )( ) r j1 U a,b[ ]j2,x,t( ) = max t 'Ît+ a,b[ ] min r j2,x,t( ), min t ''Ît,t '[ ] r j1,x,t ''( )( )( )æ èç ö ø÷ Soundness Tool Breach (a MATLAB tool) implements robustness and sensitivity-based analysis of STL formulae r j,w,t( )> 0 Þ w,t |=j r j,w,t( )< 0 Þ w,t |¹j Donze’ et al. FORMATS 2010, CAV 2013 Example mA = yA > 0 mB = yB > 0 mA Ù mB mA = yA > 0 à 2,3[ ]mA
  11. 11. Gene-Regulatory Networks AND Signal A Signal B Signal O Activating Promoter Signal A Activating Promoter Signal B Gene 1 Product (protein) Gene 1 Product (protein) Gene1Gene2 Controlled Gene Activating Promoter Desired Gene Product We consider deterministic models (Ordinary Differential Equations) These models consider n genes that produce proteins whose concentration is indicated by x1,..,xn. The dynamics is described by the non-linear ODEs: dxi dt = fi x1, , xn,k( ) = fi + x1, , xn,k( )- fi - x1, , xn,k( ) "i =1, ,n f + i is a production rate (Michelis-Menten or Hill-function dynamics) f - i is a degradation rate (linear term mxi ) A B O High High High High Low Low Low High Low Low Low Low
  12. 12. Logical Characterization of the modules
  13. 13. Logical Characterization (1) Module specification A module M is a Genetic-Regulatory network and is characterized by: • the inputs: the external transcription factors that regulate the genes of M; • the outputs: a subset of the produced proteins; • the behavior: a set of STL formulae of the form: where the formula describes the input behavior and describes the output behavior. jI ®jO, jI jO
  14. 14. 1st Row qA+ qB+ qC+ Logical Characterization (2) Example of a module: an AND GATE xC = FAND xA, xB, xc,k( ) = kAB xA n KA n + xA n xB n KB n + xB n - kC xC k = k AB ,kC,KA,KB,n( ) is tuple of 5 parameters k AB is the maximum production rate kC is the degradation rate KA,KB govern the Hill activation function n is responsible for the steepness of the Hill function Temporal Logical Characterization A B C High High High High Low Low Low High Low Low Low Low 1) 2) 3) 4) The STL formula is jI ®jO where: jI = 0, l+d[ ] xA ³qA+ Ù xB ³qB+( ) jO = à 0, d[ ] 0, l[ ] xC ³qC+( ) d = maximum delay/response time l= minumum duration true = high = above q+ false = low = below q- l +dd l
  15. 15. 1st Row qA+ qB+ qC+ Logical Characterization (2) Example of a module: an AND GATE Temporal Logical Characterization A B C High High High High Low Low Low High Low Low Low Low 1) 2) 3) 4) The STL formula is jI ®jO where: jI = 0, l+d[ ] xA ³qA+ Ù xB ³qB+( ) jO = à 0, d[ ] 0, l[ ] xC ³qC+( ) d = maximum delay/response time l= minumum duration true = high = above q+ false = low = below q- l +dd l  0,l+d[ ] xA >qA- Ù xB >qB-( )® à 0,d[ ] 0,l[ ] xC >qC-( )  0,l+d[ ] xA >qA- Ù xB £qB-( )® à 0,d[ ] 0,l[ ] xC £qC-( )  0,l+d[ ] xA £qA- Ù xB >qB-( )® à 0,d[ ] 0,l[ ] xC £qC-( )  0,l+d[ ] xA £qA- Ù xB £qB-( )® à 0,d[ ] 0,l[ ] xC £qC-( ) INPUT OUTPUT Max delay=δ Min. duration=λ High High High High Low Low Low High Low Low Low Low
  16. 16. Network of modules Hierarchical Composition Example: Half-Adder xD = bD 1+ xB KBD æ èç ö ø÷ n -aD × xD , xE = bE × xA n KAE n + xA n × xD n KDE n + xD n -aE × xE , xF = bF 1+ xA KAF æ èç ö ø÷ n -aF × xF , xG = bG × xF n KFG n + xF n × xB n KBG n + xB n -aG × xG , xS = bS × xE KES æ èç ö ø÷ n + xG KGS æ èç ö ø÷ n 1+ xE KES æ èç ö ø÷ n + xG KGS æ èç ö ø÷ n -aS × xS , xC = bC × xA n KAC n + xA n × xB n KBC n + xB n -aC × xC , xD (0) = xD0 ,xE (0) = xE0 ,xF (0) = xF0 xG (0) = xG0 ,xS (0) = xS0 ,xC (0) = xC0 ì í ï ï ï ï ï ï ï ï ï ï ï ï ï î ï ï ï ï ï ï ï ï ï ï ï ï ï A Network is a more complex module. The output of a module is piped to the input of another.
  17. 17. ExampleMaximum Delay and Minimum DurationdNet lNet d M( )= dNet /  f M( )+ b M( )+1( )  f M( ) = b M( ) = dNet lNet the length of the longest path from M to an OUTPUT module of the network the length of the longest path from M to an INPUT module of the network l M( ) = d M( )+ max l ¢M( ){ } Given a network with maximum delay and output signal duration the maximum delay for each module M in the network is: where: and the minimum duration of the output for M is: where is an edge of the network. Constraints for acyclic networks INPUT Modules OUTPUT Modules  f MAND( )= 1, b MAND( )=1 d MAND( )= dNet / 3 l MAND( )= d MAND( )+ max{l MOR( )} = dNet / 3+ lNet (M, ¢M )  f MNOT( ) = 2, b MNOT( ) = 0 d MNOT( ) = dNet /3 l MNOT( ) = d MNOT( )+ max{l MAND( ),l MOR( )} = 2dNet /3+ lNet
  18. 18. Parameter Synthesis
  19. 19. Worst-case Input Signal Problem: the modules are connected, they are not independent, so we need to characterize for each module the worst-case input signal that would assure the satisfaction of the output property. Definition An input signal ˆxI t[ ], t Î 0, T[ ] is a worst-case input signal for jI ®jO iff "k par. configuration( ) s.t. r jI , ˆxI( )³ 0 and r jO ,FOP ˆxI ,k( )( )> 0, the following property holds: - for each other input signal xI satisfying r jI ,xI( )³ 0, it holds that r jO ,FOP xI ,k( )( ) ³ r jO ,FOP ˆxI ,k( )( ) Important: the characterization of such a “worst possible input signal” depends on the structure of the target STL formula and on the system of ODE describing the network.
  20. 20. Back to the AND GATE Quantitative satisfaction of the STL Specification jIHigh,High ®jOHigh  0, l+d[ ] xA ³qA+ Ù xB ³qB+( )® à 0, d[ ] 0, l[ ] xC ³qC+( ) r jI , xA,xB{ }( )= max tÎ0, l+d[ ] min xA t[ ]-qA+ ,xB t[ ]-qB+( )( ) r jO,xC( )= maxˆtÎ 0, l[ ] min tÎ ˆt , ˆt +déë ùû xC t[ ]-qC+( )æ èç ö ø÷ ˆxA t[ ]ºqA+ ˆxB t[ ]ºqB+The worst-case signals are , xC = FAND xA,xB,xC ,k( )= bC × xA n KAC n + xA n × xB n KBC n + xB n -aC × xC FAND xA t[ ],xB t[ ],xC ,k( )³ FAND ˆxA t[ ], ˆxB t[ ], ˆxC ,k( ) xC t[ ]³ ˆxC t[ ] "t Î 0, l+d[ ] r jO,xC( )³ r jO , ˆxC( )
  21. 21. Parameter synthesis Algorithm: Inputs: • Acyclic network of modules • STL specification of the modules and of the target circuit • Parameter spaceÃÎ n Find and fix the temporal constraints for each module/gate using the target spec. Start For each each STL spec. of the module Use worst-case Input signals to compute output For each module/gate STL parameter synthesis Parameter Sets intersection End For each End For each Stop No Yes YesNo In the case of logic gates, the parameter synthesis of each module can be done analytically (exploiting the reduction to a linear set of ODEs once the input signals are fixed)
  22. 22. Results on the Half-Adder We applied the algorithm in the previous slides, to find the parameter set to implement a network of modules/gates representing an half-adder, fixing the maximum total delay to 12 time units.
  23. 23. Conclusion and Future/Current Works
  24. 24. Conclusion Summing up  We develop an approach based on two ideas: • the specification of system properties in terms of Signal Temporal Logic (STL) • the exploitation of modularity to obtain an efficient procedure to identify a set of parameters for which the network satisfies its STL specification.  Parameter synthesis for acyclic network of logic gates: we are able to identify a set of parameters satisfying STL formulae with also constraints on its response time.  Modularity allows us to synthetize parameters efficiently, processing each gate component independently.
  25. 25. Future/Current Works We are currently working on:  Integrating our approach with databases of biological components, like BioBricks, for actual combinations of gene and promoters that satisfy the constraints on parameters.  A generalization of the worst-case analysis to deal with more complex modules (e.g. feed-forward networks implementing pulse generation or a low-pass filter)  Considering the problem of dealing with more complex networks having feedback loops.  Taking into account the effects of stochasticity, for instance by exploiting moment closure techniques.
  26. 26. Thanks for your attention

×