K Practical

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K Practical

  1. 1. Section K Practical Matters
  2. 2. S/W Development Guidelines Use internal flags to enable each optimization  Flag defaults to ON after testing complete Adhere to principles of modularity  Localize declarations to relevant components Use assertions and verification routines under #ifdef Is_True_On DEBUG build enables:  Assertions  Verification routines  DevWarns DEBUG Compiler runs much slower, but catches error earlier
  3. 3. Debugging Aids Four kinds: 1. Dump out program code in between phases (the –tr??? flags) 2. Dump out symbol table in between phases (the –ts??? flags) 3. Trace facilities of analysis/optimization process (the – tt??? flags) 4. Print routines callable inside the debugger
  4. 4. Memory Management Use the mempool facility (common/util/memory.c) instead of malloc/free  Provide any number of individually-operated pools  Stack-like operation  Pop is only way to free  Manage pools based on temporal characteristics:  Permanent  PU-wise  Phase-wise  BB-wise
  5. 5. Adding a Compiler Option If not in the option groups, start with driver/OPTIONS Otherwise:  Identify option group  Edit common/com/config_* file containing the group’s option table – Introduce internal variable to store flag – If needed, introduce corresponding set flag to monitor if user has set the flag -Compiler knows not to override user’s setting  If flag’s default is not fixed, add default setting code in common/com/config.cxx Note: the -CG option group belongs in be/cg/cgdriver.cxx
  6. 6. Adding an Intrinsic Update these files in common/com: intrn_info.cxx (table to specify characteristics) wintrinsic.h wutil.cxx Front-end needs to generate it If handled by lowering to inline code or library call (NOT_CGINTRINSIC): be/com/emulate.cxx If handled by cg expansion (CGINTRINSIC): be/cg/whirl2ops.cxx be/cg/x8664/expand.cxx
  7. 7. Adding a Machine Instruction Update these files in common/targ_info/isa/x8664: Isa.cxx Isa_operands.cxx Isa_pack.cxx Isa_print.cxx isa_properties.cxx Isa_subset.cxx and common/targ_info/proc/x8664/*_si.cxx Generate the instruction in CG
  8. 8. Adding a WHIRL operator Update these files in common/com: opcode_gen_core.h opcode_gen_core.cxx Support its WHIRL generation in: common/com/wn.cxx Teach lowering and optimization phases about this new operator If present in L WHIRL, CG needs to expand it
  9. 9. Isolating Optimization Bugs Isolate program file that triggers the bug  Binary search on the .o files Working backwards, isolate the phase that causes the bug Example: triaging an optimization bug in the backend 1. Pass with –CG:opt=0 –- bug in CG 2. Pass with –PHASE:w=off -- bug in wopt 3. Pass with –PHASE:l=off – bug in LNO or LNO’s preopt 4. Pass with –LNO:opt=0 – bug in LNO 5. Pass with –PHASE:l=off:p – bug in LNO 6. Fail with –PHASE:l=off:p – bug in LNO’s preopt 7. Fail with –PHASE:l=off:w=off –CG:opt=0 – bug in VHO
  10. 10. Isolating Optimization Bugs Inside a Phase Isolate the PU that contains the bug  Turn on/off phase on individual PU and binary search Isolate the specific optimization causing the bug inside the phase  Working backwarfds, disable each optimization via a flag Isolate where in the code the specific optimization causes the bug  Use limit flag for the specific optimization and binary search  Find smallest optimization increment when bug pops up  Diff of the two compiler outputs will pinpoint the bug
  11. 11. Putting up targ_info for a Processor Relevant files in targ_info in the order of the build: isa.cxx ascii names of the instructions isa_properties.cxx List opcodes with given properties isa_subset.cxx Specify instruction subsets isa_registers.cxx Characterize the registers for the different register classes Describe the subclass of each register class isa_enums.cxx Describe modifiers to the instructions to designate different variants The modifiers are encoded into the instruction
  12. 12. Putting up targ_info for a Processor (continued) Isa_lits.cxx List various immediates supported in the instructions isa_operands.cxx Specify the operands and results of each instruction, including their types *_si.cxx Specify scheduling characteristics of each instruction isa_print.cxx Specify printing format in the assembly output for each instruction isa_pack.cxx Specify pack formats in Itanium Isa_bundle.cxx Specify instruction bundling in Itanium
  13. 13. Putting up targ_info for a Processor (continued) Isa_decode.cxx Instruction decoding information (irrelevant nowadays) isa_pseudo.cxx Encoding and decoding information for pseudo-instructions (irrelevant nowadays) abi_properties.cxx Specifies how registers are used relative to linkage convention proc.cxx Names of the target variants with different scheduling characteristics proc_properties.cxx Defines a list of processor properties and list the target variants with those properties
  14. 14. Steps to retarget to a New Processor A. Add target in top level Makefile.gsetup B. Create build directory targia32_<targ> C. Start building by setting up Makefile in each subdir 1. Build include D. In common/com, create <targ>/config_targ.h 2. Build libcmplrs 3. Build libiberty 4. Build libcomutil A. In common/targ_info, create <targ> dir’s and their files 5. Build targ_info A. Configure GNU front-end for new processor (pick target with closest MD) 6. Build cc1/cc1plus (GNU cross compiler)
  15. 15. Steps to retarget to a New Processor (continued) G. Integrate GNU front-end with libspin 1. Build libspin 2. Build cc1/cc1plus linked with libspin H. Create files in common/com/<targ> for new target 9. Build wgen 10. Build ir_tools 11. Build libelf 12. Build libelfutil 13. Build libdwarf 14. Build libunwindP
  16. 16. Steps to retarget to a New Processor (continued) H. Create files in be/cg/<targ> 15. Build be 16. Build cg 17. Build driver 18. Build wopt 19. Build ipl 20. Build lno 21. Build inline 22. Build whirl2c 23. Build ipa DONE

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