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J. parallel (synchronous) counters


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J. parallel (synchronous) counters

  1. 1.  Synchronous means : Working or moving at the same rate Having the same period and phase of oscillation or cyclic movement.
  2. 2.  Circuitmeans: a route around which an electrical current can flow, beginning and ending at the same point.
  3. 3. In this chapter we deal with synchronouscounters. From a functional point of view,synchronous counters implement finite statemachines. However, we use a syntactic definitionand show that every circuit that obeys thesesyntactic rules implements a finite state machine.Correct functionality of a synchronous countersrequires satisfaction of certain timing constraints.Most importantly, all data inputs of flip-flops mustbe stable during the critical sections. A keyadvantage of the model (in which the criticalsection and the instability interval of each flip-flopare disjoint) is that it is possible to satisfy all thetiming constraints if the clock period is sufficientlylong.
  4. 4. In the canonic form, a synchronouscounter is decomposed into three parts: (i) the flip-flops store the state, (ii) a combinational circuit computes the output, and (iii) a combinational circuit computesthe next state. Finally, we deal with the issue ofinitialization. Loosely speaking,initialization of the circuit means that theip-ops output correct and stable valuesduring the rst clock period.
  5. 5. 1. combinational gates2. nets3. flip-flops
  6. 6. A synchronous circuit is a circuit Ccomposed of combinational gates, nets,and flip-flops that satisfies the following conditions: 1. There is a net called clk that carries a clock signal. 2. The clk net is fed by an input gate. 3. The set of ports that are fed by the clk net equals the set of clock-inputs of the flip-flops. 4. Define the circuit C0 as follows: The circuit C0 is obtained by (i) deleting the clk net, (ii) deleting the input gate that feeds the clk net, and (iii) replacing each flip-flop with an output gate (instead of the port D) and an input gate (instead of the port Q). We require that the circuit C0 is combinational.
  7. 7. In parallel (synchronous)counters the input are pulses (orlevels and pulses) with certainrestrictions on pulse width andcircuit propagation delay.Therefore synchronous circuitscan be divided intosequential circuits and or pulsed sequentialcircuits.
  8. 8. In a sequential circuitwhich has flip-flops or, in someinstances, gated latches, for itsmemory elements there isa(synchronizing) periodic clockconnected to the clock inputs of all thememory elements of the circuit, tosynchronize all internal changes ofstate.
  9. 9. On the other hand in an or pulsed sequentialcircuit, such a clock is not present.Pulse mode circuits require twoconsecutive transitions between 0 and1 - that is a 0-pulseor a 1 pulse toalter the circuit’s state. A pulse -modecircuit is designed to respond topulses of certain duration; theconstant signals between the pulsesare null or spacer signals, which donot affect the circuit’s behavior.
  10. 10. 1) For pulsed sequential circuits these occur only for the duration of the respective input pulse and in some cases for duration considerably less. For clocked sequential circuits these outputs occur for the duration of the clock pulse.2) These change state at the start of the respective input or clock pulse and remain in that state until the next state of output is required.
  11. 11. A synchronous electric motor isan in which the rotation ofthe shaft is synchronized with the of the supply current;the rotation period is exactly equal toan integral number of AC cycles.Synchronous motors contain on the of themotor that create awhich rotates in time with theoscillations of the line current. The turns in step with this field, at thesame rate.