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"Accelerate Adoption of AI at the Edge with Easy to Use, Low-power Programmable Solutions," a Presentation from Lattice Semiconductor


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Hussein Osman, Consumer Segment Manager at Lattice Semiconductor, presents the "Accelerate Adoption of AI at the Edge with Easy to Use, Low-power Programmable Solutions" tutorial at the May 2019 Embedded Vision Summit.

In this talk, Osman shows why Lattice’s low-power FPGA devices, coupled with the sensAI software stack, are a compelling solution for implementation of sophisticated AI capabilities in edge devices. The latest release of the sensAI stack provides a performance increase of more than 10X compared with the previous release. This performance increase is driven by updates to the CNN IP and the neural network compiler tool, including a number of new features, such as support for 8-bit activation quantization and smart merging of layers.

For a seamless user experience, the new release expands the list of neural network topologies and machine learning frameworks supported, and automates the quantization and fraction settings processes. In addition, Lattice Semiconductor provides a comprehensive set of reference designs which include training datasets and scripts for popular machine learning frameworks, enabling easy customization. And, to speed time to market for popular use cases, the company provides full turnkey solutions for human counting, human presence detection and key phrase detection.

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"Accelerate Adoption of AI at the Edge with Easy to Use, Low-power Programmable Solutions," a Presentation from Lattice Semiconductor

  1. 1. © 2019 Lattice Semiconductor Accelerate Adoption of AI at the Edge with Easy to Use, Low-power Programmable Solutions Hussein Osman
  2. 2. © 2019 Lattice Semiconductor Rapidly Emerging Edge Computing Trend Driven by Latency, Privacy, and Bandwidth Limitations AI Edge device shipments to reach 2.5 billion annually by 2025 - Tractica Edge Networking Cloud IoT Communication Gateway Wireless / Wireline Access Core Network
  3. 3. © 2019 Lattice Semiconductor Always-on, Smart IoT Devices at the Edge Doorbells and Security Cameras Presence Detection Retail store cameras Object Counting AI Edge device shipments to reach 2.5 billion annually by 2025 - Tractica Industrial Presence Detection Object Detection Object Counting Smart Home Control Presence Detection
  4. 4. © 2019 Lattice Semiconductor Always-on, On-device AI Requirements Unmet Need for Ultra-Low Power, Scalable, and Flexible Inferencing Few mWs of Power Consumption Few mm2 of Board Area Customized Performance/Accuracy Flexible Legacy Interface Support I2C SPI PCIE Ethernet USB Neural Network Accelerator
  5. 5. © 2019 Lattice Semiconductor HARDWARE PLATFORMS IP CORES SOFTWARE TOOLS REFERENCE DESIGNS / DEMOS CNN Compact Accelerator CNN Accelerator UPduino Himax Shield – iCE40 UltraPlus FPGA Video Interface Platform – ECP5 FPGA 1 mW, 5.5 mm2, 1/16 bits 1 W, 100 mm2, 1/8/16 bits CUSTOM DESIGN SERVICES Smart CarSmart Home Smart City Smart Factory Neural Network Compiler Ultra Low Power Small Form Factor Customizable Neural Network Accelerators Face Detection Speed Sign Detection Key Phrase Detection Face Tracking Object Counting Human Presence Detection Hand Gesture Detection
  6. 6. © 2019 Lattice Semiconductor Flexible Inferencing at the Edge From under 1 mW to 1 W with Lattice sensAI HIGH-END FPGA ZONE GPU ZONE MPU ZONE MCU ZONE 0.1 1 10 100 1,000 10,000 100,000 100.0 10.0 1.0 0.1 0.001 POWER(W) PERFORMANCE (Billions of Neural Ops per second) ~ ~
  7. 7. © 2019 Lattice Semiconductor Ultra-Low Power AI Accelerator 2.15 mm x 2.55 mm Package Programmable FPGA Fabric 5,280 LUTs 120 kb Block RAM iCE40 UltraPlus I/O NVCM 8 DSP Blocks 1 Mb RAM I/O I/O DSPs ▪ Convolutional engine ▪ Power efficient ▪ Computation time I/Os ▪ 100Mbps MIPI D-PHY ▪ Hardened SPI/I2C blocks ▪ Comparator, PWM Ultra Low Power ▪ 75 uW sleep power ▪ Less than10 mW active power Programmable Fabric ▪ Flexible NN engines ▪ Input/output processing ▪ Flexible interfaces Memory ▪ NN weights/activations ▪ Sensor Data ▪ Scratchpad Performance ▪ 0.4 GOPS @ 7mW - CNN ▪ 5.75 GOPS @ 1mW - BNN
  8. 8. © 2019 Lattice Semiconductor Low Power AI Accelerator 10 mm x 10 mm Package Programmable FPGA Fabric Up to 85K LUTs ECP5 I/O, SERDES Up to 156 DSP Blocks 1-3.7 Mb Block RAM I/O I/O Small Form Factor ▪ 10x10 mm package ▪ Multiple package options Automotive-grade Support ▪ In 25 - 45K LUTs Low Power ▪ AI acceleration under 1W Compute Capability ▪ Flexible NN accelerator ▪ Support popular NN ▪ 1-16bit Sufficient data throughput and DRAM bandwidth ▪ 2-4 SERDES @ 5 Gbps Rx/Tx ▪ DDR3/3L, LPDDR2/3 @ 800 Mbps Performance ▪ 32 GOPS @ 850mW - CNN ▪ 512 GOPS @ 750mW - BNN
  9. 9. © 2019 Lattice Semiconductor Low Power sensAI Accelerator Use Cases Post Processing Preprocessing Preprocessing Stand-alone
  10. 10. © 2019 Lattice Semiconductor IP Cores Neural Network Accelerator IP CNN Compact Accelerator Key features • Optimized for iCE40 UltraPlus FPGA • Support for variable quantization (16/1) for weights and activation MEMORY (SPRAM/ EBRAM) EBRAM EBRAM EBRAM EBRAM FC EU CONTROL BINARIZER BIN ADDR GEN EBRAM EBRAM EBRAM EBRAM POOL EU EBRAM EBR:1 CONV EU EBR:2 EBRAM EBRAM CONV ADDR GEN BIN scratch storage (16 bits, 1K entries) EBR:4 EBR:4 CONV scratch storage (16 bits, 1K entries) Activation data storage (16 bits, EBRAM:4K entries, SINGLE_SPRAM: 16K DUAL_SPRAM: 32K) Control Command FIFO I/F Result Input data STORAGE ADDR GEN
  11. 11. © 2019 Lattice Semiconductor IP Cores Neural Network Accelerator IP Key features • Optimized for ECP5 FPGA • Support for variable quantization (16/1) for weights and (16/8/1) activation Convolutional Neural Network (CNN) Accelerator AXI Master CONV EU CONV EU FC EU Pooling EU Engine Pool AXI Rd Master CMD queue State Machine Control Unit Seq Gen 15 MEM 15 MEM 0 MEM 1 Seq Gen 1 Seq Gen 0 . . . . . . . . Memory Pool Sequence Program Parameter Program Control AXI bus for DRAM I/F Input Data Result Save/Load Input/Output/Intermediate Data
  12. 12. © 2019 Lattice Semiconductor Software Tools Neural Network Compiler Key features • Implement NN developed using standard frameworks into Lattice FPGAs without prior RTL experience • Rapidly analyze, simulate, and compile CNNs/BNNs for implementation on Lattice sensAI IP cores
  13. 13. © 2019 Lattice Semiconductor Now with 10X Boost in Performance Higher Frames per Second Higher Resolution Smaller Size Lower Power
  14. 14. © 2019 Lattice Semiconductor Updated User Experience Makes AI Even Easier Enhanced Demos and Reference Design In HW Debugging Capabilities Automatic quantization and fractional settings support Expanded list of NN Topologies and Machine learning frameworks
  15. 15. © 2019 Lattice Semiconductor FPGA Design Training Customizable Reference Designs NN Models Training Dataset Training Scripts ML Frameworks NN Compiler FPGA Tools NN IP System Interface Trained Model FPGA Bitstream Quantized Weights and Instructions Updated New
  16. 16. © 2019 Lattice Semiconductor Low Power, Optimized Demos Human Presence Detection ▪ Sensor: CMOS image sensor ▪ Resolution: 64x64x3 ▪ Network: VGG8 ▪ Speed: 5 frames per second ▪ Power: 7 mW on iCE40 UltraPlus ▪ Sensor: CMOS image sensor ▪ Resolution: 128x128x3 ▪ Network: VGG8 ▪ Speed: 30 frames per second ▪ Power: 850 mW on ECP5-85K Human Counting
  17. 17. © 2019 Lattice Semiconductor Expanded Partner Ecosystem Complete Product Design and Video ExpertiseDesign Partners with AI and FPGA expertise
  18. 18. © 2019 Lattice Semiconductor Market Adoption “The Lattice sensAI solutions stack lets us easily add low power, flexible AI inference support to our existing and new camera designs and get our value-added products to market faster.” – Seton Kasmir, CEO, Pixcellence, Inc.
  19. 19. © 2019 Lattice Semiconductor To Learn More about Stop by and talk to our team @ Booth 205 Visit our website @ Contact me @
  20. 20. © 2019 Lattice Semiconductor Thank you