Study Of 30W Digital Audio Amplifier with Integrated ADC: CS4525

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Study Of 30W Digital Audio Amplifier with Integrated ADC: CS4525

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  • This is a training module for the Cirrus Logic CS4525 30W Digital Audio Amplifier with integrated Analog To Digital Converter.
  • Welcome to the training module on the Cirrus CS4525 30W Digital Audio Amplifier with Integrated ADC. We will be studying the Cirrus CS4525 application configuration and its available features in the coming slides.
  • The CS4525 is a stereo analog or digital input PWM high efficiency Class D amplifier audio system with an integrated stereo analog-to-digital (A/D) converter. The stereo power amplifiers can deliver up to 15 W per channel into 8 Ω speakers. The power stage outputs can be configured as two full bridge channels (15 watts per channel) , two half-bridge channels and one full-bridge channel for 2 channel 7 W + 1 channel 15 W operation, or one parallel full-bridge channel for 1 channel 30 W operation.
  • Here we show the ADC feature of CS4525 which has 24-bit, 48kHz stereo conversion it has multi-bit architecture and it supports up to 95dB Dynamic Range. It has -88dB THD+N.
  • The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system integration. The SRC allows for a fixed PWM switching frequency regardless of incoming sample rate as well as optimal clocking for the A/D modulators.
  • The common applications of CS4525 are in Integrated Digital TV’s, Flat Panel TV Monitors, Computer/TV Monitors, Mini/Micro Shelf Systems, Digital Powered Speakers, Portable Docking Stations, Computer Desktop Audio.
  • Here is the Block diagram of CS4525 it consists of a Multi-bit Sigma-Delta ADC where Stereo analog input is feed, and a serial audio input port where the serial audio and clock are given. There is an audio processing block which has a Parametric equalizer where filtering and adaptive loudness compensation are done, it also has a 2 channel mixer and a 2.1 bass manager. Its PWM block can do an integrated sample rate conversion, this signal is buffered and amplified. It has set of registers and a hardware configuration for IIc communication, and to handle interrupts and reset. The CS4525 integrates on-chip over-current, under-voltage, and over-temperature protection and error reporting as well as a thermal warning indication and programmable fold back of the output power to allow cooling The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system integration. An on-chip oscillator driver eliminates the need for an external crystal oscillator circuit, reducing overall design cost and conserving circuit board space. The CS4525 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5 V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 V supply to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD pin
  • Here we show a procedure of how the CS4525 device is powered-up.
  • Here is a procedure for Power down of the CS4525 Device.
  • Here we explain how the CS4525 is configured in it’s software mode. All device configuration is achieved via the I²C control port. In this mode Maximum device flexibility and features are available. the CS4525 can be clocked by a stable external clock source input on the SYS_CLK pin or by a clock internally generated through the use of its internal oscillator driver circuit. The CS4525 has two configurable logic-level PWM outputs, PWM_SIG1 and PWM_SIG2. These outputs can be used as either digital input to an external PWM amplifier such as the CS4412, or as an analog input to a headphone amplifier or a line-out amplifier. The internal clock is used to synchronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate converter, and PWM modulators. The CS4525 must be informed of the nominal frequency of the supplied SYS_CLK signal or the attached crystal via the ClkFreq[1:0] bits in the Clock Config register.
  • A limited feature set is available when the CS4525 powers up in hardware mode. All device configuration is achieved via hardware control input pins, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK pin. The CS4525 will remain in a completely powered-down state until the RST pin is brought high. This input clock is used to synchronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used to determine the sample rate of the serial audio input signals in order to automatically configure the various internal filter coefficients. In this mode The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied through the serial audio input port. Analog audio input signals are supplied through the internal ADC. The input source is selected by the ADC/SP pin and can be changed at any time without causing any audible pops or clicks. In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of managing switching noise and reducing radiated emissions. Also In the hardware mode, the CS4525 operates as a 2-channel full-bridge PWM amplifier with analog or digital inputs. Both the PWM outputs and the auxiliary serial outputs are unavailable in hardware mode.
  • The CS4525 includes three Pulse Width modulators and three corresponding sample rate converters, each clocked from the external crystal or system clock applied at power-up. The SRC also allows the Pulse Width modulator output to be independent of the input serial audio clock jitter. This results in very low Jitter output and higher dynamic range.
  • This slide shows a circuit for a Half-Bridge output filter, here A transient voltage suppression circuit is implemented as an RC snubber network comprised of a resistor Rs (5.6 Ω, 1/8 W) and a capacitor Cs (680 pF). This should be placed as close as possible to the corresponding output pin. This circuit decreases the slew rate of the output signal and reduces high frequency ringing which can lead to increased EMI. The Schottky diodes D1 and D2 protect the body diodes of the output devices by conducting load current during switching transitions; these diodes must be present to ensure proper device operation.
  • This slide shows the output filter for stereo full-bridge and parallel full-bridge output configurations. Transient voltage suppression circuits are implemented as a RC snubber networks comprised of resistors Rs (5.6 Ω, 1/8 W) and capacitors Cs (680 pF). These should be placed as close as possible to the corresponding output pin. These circuits decrease the slew rate of the output signal and reduce high frequency ringing which can lead to increased EMI. The Schottky diodes protect the body diodes of the output devices by conducting load current during switching transitions; these diodes must be present to ensure proper device operation.
  • This circuit provides the necessary high-frequency filtering with a first-order passive low-pass filter that has less than 0.05 dB of attenuation at 24 kHz. It also includes a DC blocking capacitor to accommodate the analog input pins bias level. To interface 2 VRMS input signals with the CS4525’s analog inputs, an external resistor divider is required.
  • In I²S format, data is received most significant bit first one SCLK delay after the transition of LRCK and is valid on the rising edge of SCLK. The left channel data is presented when LRCK is low; the right channel data is presented when LRCK is high. In Left-Justified format, data is received most significant bit first on the first SCLK after a LRCK transition and is valid on the rising edge of SCLK. The left channel data is presented when LRCK is high and the right channel data is presented when LRCK is low. In Right-Justified format, data is received most significant bit first and with the least significant bit presented on the last SCLK before the LRCK transition and is valid on the rising edge of SCLK.
  • The CS4525 Power Calculator provides many important application-specific performance numbers for the CS4525 based on user-supplied design parameters. The Power Calculator uses first-order approximations to serve as a guideline in designing new applications featuring the CS4525. The Power Calculator assumes that all applications follow Cirrus Logic’s recommended layout considerations and guidelines for the CS4525. It is important to note that deviation from these recommendations in an application may result in a discrepancy between the calculator’s predictions and the application’s results.
  • This slide shows a Confiuration Diagram for a 2 x 7 W Stereo + 1 x 15 W Subwoofer
  • This slide shows an application configuration block diagram for 2 x 15 W Stereo + 1 x 30 W Subwoofer.
  • This slide shows an application configuration block diagram for a 2 x 30 W Stereo + 1 x 30 W Subwoofer.
  • This slide shows application configuration block diagram for 2 x 15 W Bi-Amp Stereo with Subwoofer Output.
  • Thank you for taking the time to view this presentation on CS4525. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Cyrus Logic site http://www.cirrus.com/en/products/pro/detail/P1109.html or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Study Of 30W Digital Audio Amplifier with Integrated ADC: CS4525

    1. 1. Study Of 30W Digital Audio Amplifier with Integrated ADC: CS4525 <ul><li>Source: Cirrus Logic </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>Study Of 30W Digital Audio Amplifier with Integrated ADC: CS4525 </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features: Digital, ADC, System </li></ul></ul><ul><ul><li>Application </li></ul></ul><ul><ul><li>Typical Block Diagram: Software / Hardware mode. </li></ul></ul><ul><ul><li>Application Configuration </li></ul></ul><ul><ul><li>Half-Bridge, Full-Bridge Output Filter </li></ul></ul><ul><ul><li>Analog Inputs and Serial Audio Interfaces </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>22 pages </li></ul></ul>
    3. 3. Digital Amplifier Features <ul><li>Fully Integrated Power MOSFETs </li></ul><ul><li>No Heat sink Required </li></ul><ul><ul><li>Programmable Power Fold back on Thermal Warning </li></ul></ul><ul><ul><li>High Efficiency (85%) </li></ul></ul><ul><li>> 100 dB Dynamic Range </li></ul><ul><li>< 0.1% THD+N @ 1 W </li></ul><ul><li>Configurable Outputs (10% THD+N) </li></ul><ul><ul><li>1 x 30 W into 4 Ω, Parallel Full-Bridge </li></ul></ul><ul><ul><li>2 x 15 W into 8 Ω, Full-Bridge </li></ul></ul><ul><ul><li>2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge </li></ul></ul><ul><li>Built-In Protection with Error Reporting </li></ul><ul><ul><li>Overcurrent / Undervoltage / Thermal Overload Shutdown </li></ul></ul><ul><ul><li>Thermal Warning Reporting </li></ul></ul><ul><li>PWM Popguard® for Half-Bridge Mode </li></ul><ul><li>Programmable Channel Delay for System Noise & Radiated Emissions Management </li></ul>
    4. 4. ADC Features <ul><li>Stereo, 24-bit, 48 kHz Conversion </li></ul><ul><li>Multi-bit Architecture </li></ul><ul><li>95 dB Dynamic Range (A-wtd) </li></ul><ul><li>-88 dB THD+N </li></ul><ul><li>2 Vrms Input Supports SCART </li></ul>
    5. 5. System Features <ul><li>Asynchronous 2-Channel Digital Serial Port </li></ul><ul><li>32 kHz to 96 kHz Input Sample Rates </li></ul><ul><li>Operation with On-Chip Oscillator Driver or Applied SYS_CLK at 18.432, 24.576 or 27.000 MHz </li></ul><ul><li>Integrated Sample Rate Converter (SRC) </li></ul><ul><ul><li>Eliminates Clock-Jitter Effects </li></ul></ul><ul><ul><li>Input Sample Rate Independent Operation </li></ul></ul><ul><ul><li>Simplifies System Integration </li></ul></ul><ul><li>Spread Spectrum PWM Modulation </li></ul><ul><ul><li>Reduces EMI Radiated Energy </li></ul></ul><ul><li>Low Quiescent Current </li></ul>
    6. 6. Common Applications <ul><li>Integrated Digital TV’s </li></ul><ul><li>Flat Panel TV Monitors </li></ul><ul><li>Computer/TV Monitors </li></ul><ul><li>Mini/Micro Shelf Systems </li></ul><ul><li>Digital Powered Speakers </li></ul><ul><li>Portable Docking Stations </li></ul><ul><li>Computer Desktop Audio </li></ul>
    7. 7. Typical Block Diagram
    8. 8. Power-Up Sequence <ul><li>Hold RST low until the power supplies and the input SYS_CLK are stable. </li></ul><ul><li>Bring RST high. </li></ul><ul><li>If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within 10 ms following the release of RST. </li></ul><ul><li>This operation causes the device to enter software mode and places it in power-down mode. </li></ul><ul><li>If the LVD pin is tied low and VD, VD_REG, and VA_REG are connected to 2.5 V, clear the SelectVD bit in the Power Ctrl register to indicate the 2.5 V VD supply level. </li></ul><ul><li>If VP is connected to a supply voltage less than or equal to 14 V nominal, clear the SelectVP bit in the Fold-back Configuration register to indicate the VP supply level. </li></ul><ul><li>Write the following initialization sequence to the CS4525 registers: </li></ul><ul><ul><li>– 55h to register 64h. </li></ul></ul><ul><ul><li>– 08h to register 69h. </li></ul></ul><ul><ul><li>– 00h to register 64h. </li></ul></ul><ul><li>Other desired register settings can be loaded while keeping the PDnAll bit set. </li></ul><ul><li>Clear the PDnAll bit to initiate the power-up sequence. </li></ul>
    9. 9. Power-Down Sequence <ul><li>Set the MuteChA, MuteChB, and MuteSub bits in the Mute Control register to mute the audio output. </li></ul><ul><li>Set the PDnAll bit to power-down the device. </li></ul><ul><li>If the SYS_CLK input clock mode is used, the SYS_CLK signal may now be removed. See section </li></ul><ul><li>1.1 on page 26 for more information. </li></ul><ul><li>Bring RST low to bring the device’s power consumption to an absolute minimum. </li></ul><ul><li>Remove power. </li></ul>
    10. 10. Typical Connection Diagram Software Mode
    11. 11. Typical Connection Diagram Hardware Mode
    12. 12. PWM Modulators and Sample Rate Converters <ul><li>The CS4525 includes three PWM modulators and three corresponding sample rate converters, each clocked from the external crystal or system clock applied at power-up. </li></ul><ul><li>The frequency content of the out-of-band noise generated is dependent on the PWM switching frequency. </li></ul><ul><li>To easily accommodate input sample rates ranging from 32 kHz to 96 kHz without requiring the adjustment of output filter component values, the CS4525 utilizes a sample rate converter (SRC) to keep the PWM switching frequency fixed regardless of the input sample rate. </li></ul>PWM Output Switching Rates and Quantization Levels
    13. 13. Half-Bridge Output Filter The output filter configuration of the CS4525 can greatly affect device performance. These components reduce radiated EMI, protect the output transistors of the device, attenuate the high frequency content of the output signal. The inductor L1 and capacitor C1 form a low-pass filter to remove high frequency switching content from the output signal. These values combine with the nominal load impedance of the speaker to set the cut-off frequency of the filter.
    14. 14. Full-Bridge Output Filter (Stereo or Parallel) The inductors L1 and L2 along with capacitor C1 form the low-pass filter. These values combine with the nominal load impedance of the speaker to set the cut-off frequency of the filter
    15. 15. Analog Inputs <ul><li>AINL, AINR are the two input pins where we feed the analog input signal </li></ul><ul><li>A single order passive low-pass filter is recommended to prevent high-frequency content from aliasing into the audio band due to the analog-to-digital conversion process. </li></ul><ul><li>A DC-blocking capacitor is required as the CS4525’s analog inputs are internally biased to VQ. </li></ul>Unity Gain Input Filter
    16. 16. Serial Audio Interfaces <ul><li>The CS4525 interfaces to external digital audio devices via the serial audio input port and the auxiliary/delay serial ports. </li></ul><ul><li>The serial audio input port provides support for I²S, Left-Justified and Right-Justified data formats and operates in slave mode only, with LRCK and SCLK as inputs. </li></ul><ul><li>The auxiliary/delay serial port (available in software mode only) supports I²S and Left-Justified data formats and operates in master mode only, with AUX_LRCK and AUX_SCLK as outputs. </li></ul>I²S Data Format:
    17. 17. CS4525 Power Calculator Audio Performance Value Unit Description Output Power (<1%THD) 10.2 Watts Power at <1%THD (0dB FS) per channel Output Power (7%THD) 14.2 Watts Power at 7% THD (Clipped) per channel Output Power (10%THD) 15.4 Watts Power at 10% THD (Clipped) per channel Peak Load Voltage 12.8 Volts Peak voltage across the output load Peak Load Current 1.6 Amps Peak current through the output load   Efficiency Value Unit Description Rated Power / Channel 15.4 Watts Rated output power per channel Supply Current / Channel 1.0 Amps Supply current per channel at rated power Estimated Total Supply / IC 2.1 Amps Total current from the high-power supply Heat Generated / Channel 1.7 Watts Heat generated by the CS4525 per channel Estimated Total Heat / IC 3.5 Watts Total heat generated by the CS4525 Amplifier Efficiency 89.9% % Amplifier power output vs power input
    18. 18. Configuration Diagram 2 x 7 W Stereo + 1 x 15 W Subwoofer
    19. 19. Configuration Diagram 2 x 15 W Stereo + 1 x 30 W Subwoofer
    20. 20. Configuration Diagram 2 x 30 W Stereo + 1 x 30 W Subwoofer
    21. 21. Configuration Diagram 2 x 15 W Bi-Amp Stereo with Subwoofer Output
    22. 22. Additional Resource <ul><li>For ordering the CS4525, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.cirrus.com/en/products/pro/detail/P1109.html </li></ul></ul>

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