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MC100LVEP34 Clock Generation Chip


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An Introduction to 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip

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MC100LVEP34 Clock Generation Chip

  1. 1. MC100LVEP34 Clock Generation Chip <ul><li>Source: ON Semiconductor </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>An Introduction to 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features </li></ul></ul><ul><ul><li>Logic Diagram </li></ul></ul><ul><ul><li>Timing diagram, Reset recovery time </li></ul></ul><ul><ul><li>Duty cycle skew, output-output skew </li></ul></ul><ul><ul><li>Clock Distribution Tree. </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>12 pages. </li></ul></ul>
  3. 3. Features <ul><li>35 ps Output-to-Output Skew </li></ul><ul><li>Synchronous Enable/Disable </li></ul><ul><li>Master Reset for Synchronization </li></ul><ul><li>The 100 Series Contains Temperature Compensation. </li></ul><ul><li>PECL Mode Operating Range: VCC = 2.375 V to 3.8 V </li></ul><ul><li>with VEE = 0 V </li></ul><ul><li>NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V </li></ul><ul><li>Open Input Default State </li></ul><ul><li>LVDS Input Compatible </li></ul><ul><li>Pb-Free Packages are Available </li></ul>
  4. 4. Logic Diagram
  5. 5. Timing Diagrams If the MR is de-asserted (H-L), while the Clock is still high, the outputs will follow the second ensuing clock rising edge
  6. 6. Timing Diagrams If the MR is de-asserted (H-L), after the Clock has transitioned low, the outputs will follow the third ensuing clock rising edge.
  7. 7. Reset Recovery Time CASE 1 CASE 2
  8. 8. Typical Termination for Output Driver Typical Termination for Output Driver
  9. 9. Duty Cycle Skew <ul><li>The duty cycle skew is a measure of the difference between the TPLH and TPHL propagation delays </li></ul><ul><li>Differences in TPLH and TPHL will result in pulse width distortion the duty cycle skew is sometimes referred to as pulse skew. </li></ul><ul><li>Duty cycle skew is important in applications where timing operations occur on both edges or when the duty cycle of the clock signal is critical. </li></ul>
  10. 10. Output-to-Output Skew <ul><li>Output-to-output skew is defined as the difference between the propagation delays of all the outputs of a device. </li></ul><ul><li>Typically the output-to-output skew will be smaller than the duty cycle skew for TTL and CMOS devices </li></ul><ul><li>The output-to-output skew is important in systems where either a single device can provide all of the necessary clocks or for the first level device of a nested clock distribution tree. </li></ul>
  11. 11. ECL Clock Distribution Tree <ul><li>Here we illustrates a two level clock distribution tree which produces nine differential ECL clocks on six different cards. </li></ul><ul><li>The ECLinPS E211 device gives the flexibility of disabling each of the cards individually </li></ul><ul><li>The device also provides a muxed clock input for incorporating a high speed system clock and a lower speed test or scan clock within the same distribution tree. </li></ul>
  12. 12. Additional Resource <ul><li>For ordering MC100LVEP34, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li> </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>