Welcome to the training module on Interleaved Power Factor Correction.
This training module will introduce Interleaved PFC and its key design factors.
The Power Factor is defined as the ratio between the Real Power and the Apparent Power in an AC circuit. The Real Power represents the net transferred energy transferred to the load over one complete AC cycle while the Reactive Power represents the fraction that is only temporarily stored by the load. The Real Power is the one measured and monitored for power consumption, and its associated energy being used to produce mechanical work and heating. Traditionally, the power factor is associated with the cosine of angle between the real and apparent power components. For simplicity, the apparent power can be represented as the vector sum of the real and reactive power, but in the case of non sinusoidal periodical signals, a more complex relationship between these components is considered.
A power factor correction block diagram can be divided into 3 main blocks: First, the rectifier, which provides DC voltage to the Power factor correction converter stage. Next is the Power factor correction converter itself which provides the control over the current shape and phase lag while regulating the output voltage. Finally it is the controller block. The Power factor correction converter can be implemented using different circuit topologies, each of them with their advantages and disadvantages. As it may be observed, the input is an AC supply, the output of the Power factor correction is a DC voltage. An ideal Power factor correction makes sure that its input impedance is purely resistive. This allows maximum use of usable power, or real power. The feedback signals needed for the control loop are the rectified AC voltage, input AC current and output DC voltage. The output of the control block is a Pulse Width Modulation (PWM) signal.
In this page, three of the most common topologies of Power factor correction implementation are presented. We will highlight advantages and disadvantages for each of them. These topologies are: buck, boost, and buck-boost converters. Starting with the Buck converter, the output voltage provided to the load is always less than the input terminals (also known as a step down converter). For the purpose of power factor correction, the buck converter will function in discontinuous conduction mode. The Boost converter has the output voltage greater than the input (also known as a step up converter). When using this topology for power factor correction, the current is continuous. As shown in the current diagram, Continuous Conduction Mode allows a continuous current through the inductor. The combination of the Buck-Boost converter, as the name suggests, is a combination of a buck converter and a boost converter so that the characteristics of both are achievable. The output voltage can be greater of lower that the input voltage. One disadvantage of the buck and buck-boost topologies is that the switch is not referred to ground, which makes the driver circuitry more complex. The buck-boost topology also inverts the sign of the output voltage, which brings another disadvantage when comes to a cost effective implementation of the sensing circuitry. The preferred method for implementing Power factor correction and Interleaved Power factor correction is the boost converter due to the reduced current ripple, simplicity of gate driver implementation, and also because it meets the requirements of output voltage. The discontinuous conduction mode of buck and buck-boost topologies would have a negative influence on the total harmonic distortion, or THD, and higher gate driver cost.
The boost converter’s operation is based on the energy stored in inductance L1 as shown. When the Q1 transistor is ON, the current through the inductance is rising and fly-back diode D1 stops conduction. As soon as the Q1 switch opens, there’s no path for the current that was flowing through the inductor, except diode D1, the output capacitor C3 and the load. The D1 diode closes and starts conducting since the voltage on its anode is higher than the rectified voltage of AC source. The voltage across inductance L1 reverses its sign to maintain current flow. This way, both the energy supplied by the AC source and the one previously stored in the inductor are transferred to the load and the output capacitor through diode D1. The input rectified voltage Vac and the output DC voltage Vdc are measured using resistor dividers, while the input current is measured using a shunt resistor. The role of the inductance in this power factor correction topology is essential. The physical size of the inductor increases with the power rating. Component size is one of the main reason for implementing an Interleave PFC design.
An interleaved Power factor correction consists of two boost converters sharing the same load capacitor. As we can see in the simplified schematic, if we assume we have the same inductance for each boost converter, we can see that the energy stored by the system is doubled. Since the energy stored in the inductors is a key factor for determining the output power capabilities of the system, the output power provided by a single stage Power factor correction can be provided by an Interleaved Power factor correction with much lower inductance values. Lower inductance means smaller inductors for a given power rating.
A simplified block diagram of a dual phase interleaved PFC is shown. As mentioned earlier, a second PFC converter is added sharing the same inputs and outputs.
The difference between an Interleaved Power factor correction and a single stage Power factor correction is that two inductors are used for energy storage. Since energy should be distributed equally, a load balancing controller is added to the interleaved Power factor correction to make sure the system compensates for variation in inductance values or feedback circuits. The Interleaved Power factor correction system has three main compensators: one for voltage, one for current and one for load balance. Additionally, a feed-forward controller is implemented to compensate for sudden input voltage changes. The voltage error controller makes sure that the output voltage is not affected by load variations. The inputs to this controller are DC output voltage and the corresponding reference. The output of this controller is the current compensator reference. The current error controller regulates the phase and shape of the input current. This input current is the sum of both inductor currents, and it is measured using a shunt resistor. The output of this controller is a Pulse Width Modulation (PWM) duty cycle, which will be applied to the power MOSFETS. To balance the currents through both inductors, a Load Balance Loop is implemented. The inputs to this compensator are the two currents I m1 and I m2 . If these currents are different, an inbalance is detected. The PI controller will regulate this error and adjust the MOSFETs’ duty cycles. The output of the load balance control loop will be a duty cycle correction term (or delta PWM), which is subtracted from ‘PWM1’ to get the final duty cycle of the first boost converter, and it is added to ‘PWM2’ to determine the balanced duty cycle of the second boost converter.
The I Power factor correction reference design board can be divided into 6 main functional blocks: the Power factor correction boost circuitry, the AC input block, the power supply block, the fault circuitry block and user’s interface and programming block. The two inductors can be seen for both stages, and MOSFETS with their respective diodes are mounted underneath the board with a heatsink for better heat dissipation.
This is a brief description about component selection for the Interleaved Power factor correction Reference Design. For the semiconductor components selection, voltage and current rating is important. Besides power rating, conduction and commutation losses are also important factors for component selection. These losses will determine the overall efficiency of the system. Semiconductor components’ losses represent about half of the total system losses. The inductance selection is also related to the output power rating. The higher the output power, the bigger the inductance will be. Another aspect to consider in the inductor selection is the required input current ripple. The output capacitor is chosen so that the output voltage ripple is within specifications. It also depends on the minimum holdup time so that controllers can act before the output capacitor loses its charge. The Effective Series Resistance (ESR) of the capacitor also affects the output voltage ripple. Therefore, the capacitor with the lowest possible ESR is recommended. The ESR of the capacitor can be lowered by coupling two capacitors in parallel if the board layout dimensions permit it.
Interleaved Power factor correction allows a more efficient power factor correction design. It also offers space savings solutions. Interleaved Power factor correction also reduces output current ripple since two inductors are sharing one load at different times. dsPIC ® digital signal controllers combine the right set of peripherals and computational power to enable Interleaved Power factor correction control with a single device. This reference design offers a starting platform for these types of applications and the modular design of the software makes it easy to understand and easy to add other functions.
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Interleaved Power Factor Correction
Interleaved Power Factor Correction (IPFC) <ul><li>Source: M ICROCHIP </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>To introduce Interleaved PFC and its key design factors </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Introduction to Power Factor Correction </li></ul></ul><ul><ul><li>IPFC Design Overview </li></ul></ul><ul><ul><li>IPFC Reference Design </li></ul></ul><ul><ul><li>Conclusion </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>13 pages </li></ul></ul>
Introduction to PFC <ul><li>cos( Φ ) = power factor </li></ul>Φ Φ Un-utilized power Applied Voltage S P Q Φ Resulting Current
IPFC Design Overview Buck Converter V 1 S D L C - + + - i V 2 V 1 i V 2 < V 1 0 - ω t ω t Boost Converter S D L C - + + - i V 1 V 2 V 1 i V 2 > V 1 ω t ω t 0 S D L C - + - + i V 1 V 2 0 ω t Buck-Boost Converter V 1 i V 2 < V 1 V 2 > V 1 ω t
IPFC Design Overview PFC MOSFET LIVE_GND + - ~ ~ Vac ~ C2 R1 R2 R4 R5 R3 R6 R sense -HV_BUS +HV_BUS C1 C4 L1 Q1 D1 PWM1H |V AC | Sense V DC Sense I AC Sense C3 Primary (Live) Side PFC MOSFET Boost Diode PFC Inductor
IPFC Design Overview 90 -265V AC PWM1H I s1 PWM1L I L2 I s2 I D1 PFC output I C I IN I L1 I D2 I OUT
User Interface dsPIC ® DSC PIM Interleaved PFC boost circuitry AC input circuitry Fault Circuitry 12V and 3.3V Power Supply IPFC Reference Design
<ul><li>Semiconductor selection </li></ul><ul><ul><li>Voltage and current rating </li></ul></ul><ul><ul><li>Conduction and commutation losses </li></ul></ul><ul><li>Inductance selection </li></ul><ul><ul><li>Power output rating </li></ul></ul><ul><ul><li>Input current ripple </li></ul></ul><ul><li>Capacitor selection </li></ul><ul><ul><li>Output voltage ripple (holdup time) </li></ul></ul><ul><ul><li>ESR value </li></ul></ul>IPFC Reference Design
Conclusion <ul><li>IPFC represents a cost and space efficient solution VS single stage PFC (considering a certain power limit) </li></ul><ul><li>IPFC reference design using dsPIC ® DSC offers the possibility of high integration factor </li></ul>
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