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Cyclone III FPGA Overview Part2


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Overview of the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family

Published in: Technology

Cyclone III FPGA Overview Part2

  1. 1. Cyclone III FPGA Overview Part II <ul><li>Source: Altera Corporation </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module will overview the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Give some insight into what new applications and capabilities features provide </li></ul></ul><ul><li>Contents </li></ul><ul><ul><li>25 pages </li></ul></ul><ul><li>Duration </li></ul><ul><ul><li>20 Minutes </li></ul></ul>
  3. 3. Memory Interfaces That Automatically Calibrate, Track, and Adjust  <ul><li>Intellectual property (IP) auto calibrates for process differences </li></ul><ul><ul><li>For both FPGA and memory </li></ul></ul><ul><ul><li>Removes timing uncertainties </li></ul></ul><ul><li>Monitors voltage and temperature variations </li></ul><ul><ul><li>Adjusts resynchronization phase (PLL output) </li></ul></ul><ul><ul><li>Does not interrupt operation </li></ul></ul><ul><ul><li>Supports DDR, DDR2, QDR II memories </li></ul></ul>
  4. 4. MegaCore Ease of Use <ul><li>Configures Altera controller and physical interface megafunction PHY </li></ul>
  5. 5. Full Rate Controller
  6. 6. Half Rate Controller <ul><li>Simplify design requirements by halving application side frequency and doubling data width </li></ul><ul><li>Example: 75MHz Nios II core operating with 150 MHz DDR2 memory </li></ul><ul><li>  </li></ul>
  7. 7. Dedicated Differential Output Buffers <ul><li>Dedicated LVDS Output Buffers on the left and right banks </li></ul><ul><ul><li>Increased performance, 840 Mbps </li></ul></ul><ul><ul><li>No external resistors required </li></ul></ul><ul><li>Improved LVDS Input Buffers on all banks </li></ul><ul><ul><li>Increased performance, 875 Mbps   </li></ul></ul>
  8. 8. OCT With Calibration <ul><li>Output buffer impedance may vary slightly due to PVT </li></ul><ul><li>With OCT Calibration, after configuration the output buffer impedance is automatically adjusted to match two external resisters (RUP & RDN), which are either 50 Ohms or 25 Ohms </li></ul><ul><li>Designer uses Quartus II software assignment editor to make a <Termination> assignment, with a value of <Series 50 Ohms with Calibration> or <Series 25 Ohms with Calibration > </li></ul>
  9. 9. Cyclone III I/O Interface Guidelines <ul><li>Cyclone III devices can drive out and receive 1.2V - 3.3V signals directly </li></ul><ul><ul><li>Drive out 3.3V LVTTL at up to 8mA and 3.3V LVCMOS at up to 2mA </li></ul></ul><ul><li>For higher drive strengths at 3.3V and PCI/PCI-X interfaces use 3.0V VCCIO </li></ul><ul><ul><li>Cyclone III 3.0V I/O standards meet the 3.3V I/O standards specifications defined by EIA/JEDEC Standard JESD8-B </li></ul></ul>
  10. 10. Clocking Resources <ul><li>Clock routing resources </li></ul><ul><ul><li>Up to 20 global clocks </li></ul></ul><ul><ul><li>Global clock routing can also be used for global signals </li></ul></ul><ul><ul><li>Powered down when not in use to save power </li></ul></ul><ul><li>Full-featured and robust PLLs </li></ul><ul><ul><li>Up to four low-jitter (200 ps) PLLs </li></ul></ul><ul><ul><li>Five programmable outputs per PLL </li></ul></ul><ul><ul><li>Wide frequency range of 5 to 440 MHz </li></ul></ul><ul><ul><li>Dynamically change both frequency and phase </li></ul></ul><ul><ul><li>Cascadable to allow broader frequency generation </li></ul></ul>
  11. 11. Cyclone III: PLLs
  12. 12. Cascading PLLs
  13. 13. PLL Dynamic Phase Adjustment <ul><li>Dynamic adjustment of PLL phase setting </li></ul><ul><li>Increase / decrease 1 step at a time </li></ul><ul><ul><li>Step increments depend on PLL configuration </li></ul></ul>
  14. 14. Clock Switch Over <ul><li>Automatically switch from 1 clock to another in the event a clock stops </li></ul><ul><li>Manually switch from 1 clock source to another </li></ul>
  15. 15. PLL Modes
  16. 16. PLLs: Maximum System Integration <ul><li>Low Cost </li></ul><ul><ul><li>Up to 10 internal & 2 external clocks from 1 clock source </li></ul></ul><ul><ul><li>Support for low cost 5 MHz clock inputs </li></ul></ul><ul><li>Flexibility </li></ul><ul><ul><li>Support multiple or unknown input frequencies in </li></ul></ul><ul><ul><li>Display application using dynamic reconfiguration </li></ul></ul><ul><ul><li>PLL cascading feature without going off chip </li></ul></ul><ul><li>External memory interface support </li></ul><ul><ul><li>X72 DDR/DDR2 interfaces using a single PLL </li></ul></ul><ul><ul><li>Dynamic phase adjustments for DQS capture alignment </li></ul></ul>
  17. 17. Cyclone III: Clocking and PLLs
  18. 18. Configuration Mode Overview
  19. 19. Understanding Configuration Timing <ul><li>Application with fast “Wake-up” time specification needs to utilize fast POR time and fast configuration modes </li></ul><ul><li>POR time and configuration time user configurable with mode select pins(MSEL3..0) </li></ul><ul><li>Fast POR option requires fast* Vcc ramp </li></ul>
  20. 20. Remote System Upgrade
  21. 21. Programming Flash in System <ul><li>Program or examine Flash device from Quartus II programmer window </li></ul><ul><ul><li>Cyclone III works as a Flash programmer with Flash loader SOF </li></ul></ul><ul><ul><li>Quartus II downloads SOF automatically & programs Flash </li></ul></ul><ul><li>Eliminates additional hardware and software for on board Flash programming </li></ul><ul><ul><li>Unique tool for Altera </li></ul></ul>
  22. 22. Cyclone III Family
  23. 23. Nios II Embedded Processor <ul><li>Choose the exact set of CPUs, peripherals, and memory you need for your application </li></ul><ul><ul><li>Achieve over 160 DMIPs of performance </li></ul></ul><ul><ul><li>Build custom instructions </li></ul></ul><ul><ul><li>Accelerate with hardware—C2H compiler automatically converts C subroutines into hardware for Nios II embedded processor </li></ul></ul><ul><li>Low cost </li></ul><ul><ul><li>Integrate your peripherals and microprocessor into a single chip </li></ul></ul><ul><ul><li>Support for multiple processors in a single device </li></ul></ul><ul><ul><li>Implement a processor on a Cyclone III FPGA </li></ul></ul>
  24. 24. Quartus II Design Software <ul><li>Industry-leading software for performance and productivity </li></ul><ul><ul><li>Supports all Cyclone III devices in free Web Edition </li></ul></ul><ul><ul><ul><li>Including the EP3C120, largest FPGA in its class </li></ul></ul></ul><ul><li>Key features </li></ul><ul><ul><li>PowerPlay technology to reduce power up to 25 percent </li></ul></ul><ul><ul><li>TimeQuest timing analyzer for easy timing closure </li></ul></ul><ul><ul><li>DSP Builder to rapidly bring your DSP design into hardware </li></ul></ul><ul><ul><li>SOPC Builder to rapidly and easily build whole systems </li></ul></ul>
  25. 25. Cyclon III Base Kits <ul><li>Cyclone III FPGA Start Kit </li></ul><ul><ul><li>Cyclone III EP3C25F324 FPGA </li></ul></ul><ul><ul><li>HSMC connector </li></ul></ul><ul><ul><li>On-board memories </li></ul></ul><ul><ul><li>256 Mbit DDR </li></ul></ul><ul><ul><li>1 Mbyte Sync SRAM </li></ul></ul><ul><ul><li>16 Mbyte Flash </li></ul></ul><ul><li>Cyclone III Dev Kits </li></ul><ul><ul><li>Cyclone III EP3C120F780 FPGA </li></ul></ul><ul><ul><li>2x HSMC connector </li></ul></ul><ul><ul><li>10/100/1000 Ethernet </li></ul></ul><ul><ul><li>On-board memories </li></ul></ul><ul><ul><li>256Mbit DDR2 </li></ul></ul><ul><ul><li>8 Mbyte Sync SRAM </li></ul></ul><ul><ul><li>64 Mbyte Flash </li></ul></ul>Figure 1 Start Kit Dev Kit
  26. 26. Additional Resource <ul><li>For ordering the Cyclone III family FPGA , please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><li> </li></ul>