Cyclone III FPGA Overview Part I <ul><li>Source: Altera Corporation  </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module will overview the major features of the Cyclone III family ...
Unprecedented Combination <ul><li>Low power </li></ul><ul><ul><li>TSMC 65-nm low-power process </li></ul></ul><ul><ul><li>...
Meeting the Needs of  Emerging High-Volume Applications
The Significance of Power <ul><li>Challenges </li></ul><ul><ul><li>Thermal management </li></ul></ul><ul><ul><li>Fixed pow...
Low Power: Process Optimizations
Process Technology Power Optimization
Power-Aware Design With Quartus II Software
Cyclone III Key Architectural Features
On-Chip Memory Enhancements
Memory Optimizations <ul><li>Memory Optimizations Increased memory block size </li></ul><ul><ul><li>Allows for increased m...
Embedded Multiplier Functionality <ul><li>Up to 260-MHz performance </li></ul><ul><li>Supports full-precision 18-bit or 9-...
18-bit Multiplier Capacity
DSP Advantages <ul><li>Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP...
H.264 Encoder Block Diagram
Enable Low-Cost H.264 Encoding
I/O Pin Features <ul><li>Variety of I/O Standards </li></ul><ul><ul><li>HSTL, SSTL Class I and II </li></ul></ul><ul><ul><...
Cyclone III I/O Enhancements
Additional Resource <ul><li>For ordering the Cyclone III family FPGA , please click the part list or </li></ul><ul><li>Cal...
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Cyclone III FPGA Overview Part1

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Overview of the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family

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Cyclone III FPGA Overview Part1

  1. 1. Cyclone III FPGA Overview Part I <ul><li>Source: Altera Corporation </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module will overview the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Provide an overview of the main new features and enhancements of the Cyclone III FPGA family </li></ul></ul><ul><li>Contents </li></ul><ul><ul><li>18 pages </li></ul></ul><ul><li>Duration </li></ul><ul><ul><li>20 Minutes </li></ul></ul>
  3. 3. Unprecedented Combination <ul><li>Low power </li></ul><ul><ul><li>TSMC 65-nm low-power process </li></ul></ul><ul><ul><li>Quartus ® II software power-aware design flow </li></ul></ul><ul><ul><li>120K logic elements (LEs) under ½ W static </li></ul></ul><ul><li>High functionality </li></ul><ul><ul><li>Densities ranging from 5K to 120K Les </li></ul></ul><ul><ul><li>Up to 4Mbits of embedded memory </li></ul></ul><ul><ul><li>Up to 288 embedded multipliers for digital signal processing (DSP) </li></ul></ul><ul><li>Low cost </li></ul><ul><ul><li>First low cost 65nm FPGA </li></ul></ul><ul><ul><li>Free Quartus II web edition software </li></ul></ul>
  4. 4. Meeting the Needs of Emerging High-Volume Applications
  5. 5. The Significance of Power <ul><li>Challenges </li></ul><ul><ul><li>Thermal management </li></ul></ul><ul><ul><li>Fixed power budgets </li></ul></ul><ul><ul><li>Battery life </li></ul></ul><ul><li>Cyclone III FPGAs </li></ul><ul><ul><li>Allow you to do more with less power </li></ul></ul>
  6. 6. Low Power: Process Optimizations
  7. 7. Process Technology Power Optimization
  8. 8. Power-Aware Design With Quartus II Software
  9. 9. Cyclone III Key Architectural Features
  10. 10. On-Chip Memory Enhancements
  11. 11. Memory Optimizations <ul><li>Memory Optimizations Increased memory block size </li></ul><ul><ul><li>Allows for increased memory capacity </li></ul></ul><ul><li>Higher memory-to-logic ratio </li></ul><ul><ul><li>Implement packet buffers </li></ul></ul><ul><ul><li>Integrate larger data and instruction caches for embedded processors </li></ul></ul><ul><ul><li>Integrate larger FIFO buffers </li></ul></ul><ul><li>Optimized memory-to-multiplier ratio for intensive processing applications </li></ul><ul><ul><li>Video line buffers </li></ul></ul><ul><ul><li>Video and image processing </li></ul></ul>
  12. 12. Embedded Multiplier Functionality <ul><li>Up to 260-MHz performance </li></ul><ul><li>Supports full-precision 18-bit or 9-bit mode </li></ul><ul><ul><li>One 18-bit or two 9-bit multipliers per block </li></ul></ul>
  13. 13. 18-bit Multiplier Capacity
  14. 14. DSP Advantages <ul><li>Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP functions </li></ul><ul><ul><li>Integrate multiple DSP devices into a single Cyclone III FPGA </li></ul></ul><ul><ul><li>Process multiple signal data streams at lower cost per channel than dedicated DSP devices </li></ul></ul>
  15. 15. H.264 Encoder Block Diagram
  16. 16. Enable Low-Cost H.264 Encoding
  17. 17. I/O Pin Features <ul><li>Variety of I/O Standards </li></ul><ul><ul><li>HSTL, SSTL Class I and II </li></ul></ul><ul><ul><li>LVDS, RSDS, Mini-LVDS, PPDS </li></ul></ul><ul><ul><li>LVCMOS </li></ul></ul><ul><ul><li>LVTTL </li></ul></ul><ul><ul><li>LVPECL </li></ul></ul><ul><ul><li>PCI, PCI-X </li></ul></ul><ul><li>3.3-V compatible </li></ul><ul><li>On-chip termination </li></ul><ul><li>Adjustable slew rates </li></ul><ul><li>Eight banks in every device in the family </li></ul><ul><ul><li>Each can implement any supported I/O standard </li></ul></ul><ul><li>Dedicated memory interfaces </li></ul><ul><ul><li>QDR II, DDR, and DDR2 </li></ul></ul>
  18. 18. Cyclone III I/O Enhancements
  19. 19. Additional Resource <ul><li>For ordering the Cyclone III family FPGA , please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><li>http://www.altera.com/products/devices/cyclone3/cy3-index.jsp </li></ul>

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