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3.3 V ECL Programmable Delay Chip MC100EP196 <ul><li>Source: ON Semiconductor </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>3.3   V   ECL   Programmable   Delay   Chip </li></ul></ul><ul><li>Outl...
Features  <ul><li>Maximum Frequency > 1.2 GHz Typical </li></ul><ul><li>PECL Mode Operating Range: VCC = 3.0 V to 3.6 V wi...
Emitter-Coupled Logic  <ul><li>ECL,   is   a   Logic   family   in   which   current   is   steered   through   bipolar   ...
Logic Diagram
ECL Clock Distribution Technique ECL Clock Distribution Tree ECL to TTL Clock Distribution Mixed ECL and TTL Distribution
Using the FTUNE Analog Input <ul><li>The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable g...
Cascading Multiple EP196s
Duty Cycle Skew <ul><li>Reductions   in   system   clock   skew   allow   designers   to   increase   the   performance   ...
Multi−Channel De-skewing <ul><li>To de skew multiple signal channels, each channel can be sent through each EP196. </li></...
Additional Resource <ul><li>For ordering MC100EP196, please click the part list or </li></ul><ul><li>Call our sales hotlin...
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3.3 V ECL Programmable Delay Chip MC100EP196

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3.3 V ECL Programmable Delay Chip

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3.3 V ECL Programmable Delay Chip MC100EP196

  1. 1. 3.3 V ECL Programmable Delay Chip MC100EP196 <ul><li>Source: ON Semiconductor </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>3.3 V ECL Programmable Delay Chip </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features </li></ul></ul><ul><ul><li>Emitter-Coupled Logic </li></ul></ul><ul><ul><li>ECL Clock Distribution Technique </li></ul></ul><ul><ul><li>Logic Diagram and Duty Cycle Skew </li></ul></ul><ul><ul><li>Multi−Channel De-skewing </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>11 pages </li></ul></ul>
  3. 3. Features <ul><li>Maximum Frequency > 1.2 GHz Typical </li></ul><ul><li>PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0V </li></ul><ul><li>NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V </li></ul><ul><li>Open Input Default State </li></ul><ul><li>Safety Clamp on Inputs </li></ul><ul><li>A Logic High on the ENbar Pin Will Force Q to Logic Low </li></ul><ul><li>D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs </li></ul><ul><li>VBB Output Reference Voltage </li></ul><ul><li>Pb-Free Packages are Available </li></ul>
  4. 4. Emitter-Coupled Logic <ul><li>ECL, is a Logic family in which current is steered through bipolar transistor to implement logic functions. </li></ul><ul><li>This particular circuit is of one 4-input OR/NOR gate. Standard voltages for this circuit are -5.2 volts (VEE) and ground (VCC). </li></ul><ul><li>The bias circuit at the right side, consisting of one transistor and its associated diodes and resistors, can handle any number of gates in a single IC package </li></ul>
  5. 5. Logic Diagram
  6. 6. ECL Clock Distribution Technique ECL Clock Distribution Tree ECL to TTL Clock Distribution Mixed ECL and TTL Distribution
  7. 7. Using the FTUNE Analog Input <ul><li>The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities. </li></ul><ul><li>The level of resolution obtained is dependent on the voltage applied to the FTUNE pin. </li></ul><ul><li>To provide this further level of resolution the FTUNE pin must be capable of adjusting the additional delay finer than the 10 ps. </li></ul>Typical EP196 Delay versus FTUNE Voltage
  8. 8. Cascading Multiple EP196s
  9. 9. Duty Cycle Skew <ul><li>Reductions in system clock skew allow designers to increase the performance of their designs. </li></ul><ul><li>ECL logic technologies offer a number of advantages for reducing system clock skew over the alternative CMOS and TTL technologies. </li></ul><ul><li>The skew introduced by logic devices can be divided into three parts: duty cycle skew, output-to-output skew and part-to-part skew. </li></ul><ul><li>The duty cycle skew is a measure of the difference between the TPLH and TPHL propagation delays. </li></ul><ul><li>Output-to-output skew is defined as the difference between the propagation delays of all the outputs of a device. </li></ul>Duty Cycle Skew Output-to-Output Skew
  10. 10. Multi−Channel De-skewing <ul><li>To de skew multiple signal channels, each channel can be sent through each EP196. </li></ul><ul><li>One signal channel can be used as reference and the other EP196s can be used to adjust the delay to eliminate the timing skews. </li></ul>
  11. 11. Additional Resource <ul><li>For ordering MC100EP196, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http:// www.onsemi.com/PowerSolutions/product.do?id =MC100EP196 </li></ul></ul><ul><li>Visit Element 14 to post your question </li></ul><ul><ul><li> www.element-14.com </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>

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