Prof. A.B Department of Electrical and Computer Engineering Spring’10
EECE 321 – Computer Organization
Project – Machine Problem 1: Modeling Memory in VHDL [10 points]
Throughout this semester, you will be working on your course project in pieces through a set of machine problems which
be released on a regular basis. At the end of the semester, you will assemble the blocks you designed in these machine
problems to implement a pipelined MIPS processor (more details to follow). So make sure you save your designs and
document them in order to use them later. Your final grade on the project will be the sum of the grades you accumulate on
the machine problems. All machine problems must be done using Modelsim version 6.5d. Follow the link on other
ECE section web site for more information.
In the first machine problem (MP1), you will learn how to model memory using VHDL. Please refer to the two VHDL
source files auxiliary.vhd and mem_tb.vhd that are provided along with MP1. The file auxiliary.vhd is a VHDL package
containing some user-defined constants, data types, functions, and procedures that you frequently need when performing
memory operations. You can add your own functions to this package as needed. The file mem_tb.vhd contains a test bench
for memory which you can use to experiment with.
The following is a description of the contents of these two files.
• MIPS_WORD_SIZE_IN_BYTES is a constant that refers to the number of BYTES within a WORD in MIPS.
• MIPS_WORD is a data type that models a 32-bit word in MIPS. It is basically a 32-bit std_logic_vector. To
define a variable in VHDL of type MIPS_WORD, use
VARIABLE word : MIPS_WORD;
The same applies for defining a signal in VHDL.
• MEM_ARRAY is a data type which models an array whose elements are MIPS_WORDs. To define a memory
that contains 64 words, use
VARIABLE mem : MEM_ARRAY(1 to 64);
• The procedure init_mem initializes memory from an external input file. The format of the input file is as follows:
Each line contains two fields separated by a white space. The first field is an address in hex format. The address is
composed of 8 hexadecimal digits. The second field contains the data corresponding to that address, again in
hexadecimal. init_mem reads this file and initialize memory, writing the data at the corresponding locations, and
filling zeros in all other locations that may not be specified in the input file.
• The procedure copy_mem_2_file does the opposite of init_mem. It takes a snapshot of memory and writes its
contents into an external file, again in the same format defined above.
• The function load_word returns the contents of memory at some address in the form of a MIPS_WORD as
• The procedure store_word stores a word into memory at some address.
• The procedures read_hex_2_natural and read_hex_2_word are auxiliary functions used in parsing a line from a
file and translating it from hexadecimal into a decimal number or a MIPS_WORD.
• The file starts by loading some IEEE packages.
• Next, the auxiliary package defined above is loaded.
• A dummy entity is defined, followed by an architecture.
• The architecture contains one simple process which you can modify to perform various memory operations.
• A memory variable mem is defined within this process. The memory contains 64 MIPS words.
• Two constants are defined to provide paths to an input file used to initialize memory and output file used to take a
snapshot of memory after performing some store operations.
• The statement init_mem(in_fname, mem) initializes memory from the input file specified by in_fname.
• The following loop loads the contents of memory one at a time and prints the contents to the output console (just
for demonstration purposes).
• The next three sets of statements before the second loop perform three store operations to memory. Data 0x22 is
written to address 0x4, data 0x33 is written to address 0xC, and data 0x44 is written to address 0x14. Note the
syntax in VHDL how to specify literals in various bases:
12343 -- base 10 integer literal
2#10011110# -- base 2 (binary) integer literal
8#720# -- base 8 (octal) integer literal
16#FFFF0ABC# -- base 16 (hex) integer literal
• The next for loop simply prints the new contents of memory onto the output console
• The statement copy_mem_2_file(out_fname, mem) prints the contents of memory into an external file.
Your tasks in this machine problem are:
• Understand the various functions and procedures defined in auxiliary.vhd and how they are used in mem_tb.vhd.
• Create a directory in your system called mp1. Under mp1, create three subdirectories: mti, src, io.
Create a VHDL project called mp1.prj under mp1mti. Then, add all your VHDL source files (i.e., with
extensions .vhd) under mp1src. Create a text file called mem_input_file.txt and save the data shown on the
next page in this file. Save mem_input_file.txt under mp1io. Make sure you do not have white spaces at the
end of the file.
• Modify mem_tb.vhd to create a memory that has 32 MIPS words. Initialize this memory from an external file
whose format is as described above. Then sort the contents of memory in ascending order. The sorted data must
then be written back to memory. The output file as a result of your simulation will automatically be written to
• Deliverables: The whole VHDL project directory.
• mti includes mp1.prj
• src includes all your source files
• io includes all your input and output data files