Universal Reconfigurable Processing Platform for Space Presented by   Dorian Seagrave  Gordonicus LLC
Introduction  MAPLD  2009 Gordonicus LLC <ul><li>An increasing number of spacecraft system engineers and scientists are de...
Features <ul><li>Reconfigurable State-of-the-Art High Speed Data Processing Capabilities </li></ul>MAPLD  2009 Gordonicus ...
LEON3FT  Processing Applications   <ul><li>Guidance, Navigation and Control  (GNC) </li></ul><ul><li>Control and Data Hand...
Xilinx  Processing Applications <ul><li>High Speed DSP Algorithm Processing </li></ul><ul><li>Image Processing  </li></ul>...
SPECIFICATIONS <ul><li>5 PROCESSORS </li></ul><ul><li>LEON3FT ASIC </li></ul><ul><li>AeroFlex UT699 SPARC TM  V8/LEON 3FT ...
LEON3FT PROCESSOR & MEMORY <ul><li>LEON 3FT </li></ul><ul><li>AeroFlex UT699  </li></ul><ul><li>SPARC TM  V8 </li></ul><ul...
MAPLD  2009 Gordonicus LLC LEON3FT PROCESSOR & MEMORY LEON3FT Aeroflex UT699 2MByte SRAM (Internal EDAC ) 32KB PROM 1GByte...
Xilinx QV4 FX60 FPGAs  & MEMORY <ul><li>Quad redundant or independent PPC processing  </li></ul><ul><li>Mixed operating sy...
MAPLD  2009 Gordonicus LLC Xilinx QV4 FX60 PPC 405 PPC 405 Xilinx QV4 FX60 XILINX PPC405 PROCESSORS & MEMORY PPC 405 512MB...
Xilinx  DSP Processing Architecture MAPLD  2009 Gordonicus LLC PPC1 PPC3 PPC0 PPC2 <ul><li>4 Designs =  </li></ul><ul><li>...
Xilinx Reconfiguration MAPLD  2009 Gordonicus LLC A Singe Node can be reconfigured with PPC1 PPC3 PPC0 PPC2 Bottom Xilinx ...
STANDARD INTERFACES <ul><li>CompactPCI </li></ul><ul><li>Console Port Async UART </li></ul><ul><li>1553 </li></ul><ul><li>...
CompactPCI MIL-STD-1553 A/B  LEON3FT Console Port MAPLD  2009 Gordonicus LLC
SpaceWire Ports MAPLD  2009 Gordonicus LLC LEON3FT SpW Router  5 Port SpW Router  5 Port RTAX 200Mbps  Configurable 200/10...
Configurable I/O <ul><li>What if my instrument interface is not SpaceWire?  </li></ul><ul><li>What if I need a custom inte...
73 User Defined I/O  MAPLD  2009 Gordonicus LLC LVDS  OR   RS422 LEON3FT F R O N T P A N E L C P C I P 2 Xilinx 39  User D...
Development & Debug Ports   <ul><ul><li>LEON 10T/100 Ethernet MII Interface  (FRONT Panel or Backplane) </li></ul></ul><ul...
RTAX 2000 CONFIGURATIONS <ul><li>CG624 Package Supports ALDEC RTAX development Suite. </li></ul><ul><li>Flexible architect...
MAPLD  2009 Gordonicus LLC
512MB   512MB   512MB   MAPLD  2009 Gordonicus LLC Application  RTAX SpW  Router DownLink0 512MB   SpaceWire SpaceWire SpW...
Availability <ul><li>Contact Aeroflex Colorado Springs </li></ul>MAPLD  2009 Gordonicus LLC
Future   …. MAPLD  2009 Gordonicus LLC Xilinx SIRF V5 Xilinx SIRF V5
Next Effort MAPLD  2009 Gordonicus LLC LEON3FT  16 MBytes EEPROM 8 Port SpW Router 16 GBytes FLASH 1 GByte SDRAM 1553 3U c...
Gordonicus LLC  www.gordonicus.com <ul><li>Hardware </li></ul><ul><ul><li>Gordon Seagrave </li></ul></ul><ul><ul><li>[emai...
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Universal Reconfigurable Processing Platform For Space Rev Voice4

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MAPLD 2009 Presentation of a universal reconfigurable multi processor hardware platform for space

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Universal Reconfigurable Processing Platform For Space Rev Voice4

  1. 1. Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC
  2. 2. Introduction MAPLD 2009 Gordonicus LLC <ul><li>An increasing number of spacecraft system engineers and scientists are demanding: </li></ul><ul><ul><ul><ul><li>More processing power </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Flexible architecture </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Standard / COTS communication interfaces </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Multiple Mission Modes / Reconfigurability </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Small form factor </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Mission hardware reuse </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Low power </li></ul></ul></ul></ul><ul><ul><ul><ul><li>High speed SERDES </li></ul></ul></ul></ul><ul><ul><ul><ul><li>High Reliability </li></ul></ul></ul></ul>
  3. 3. Features <ul><li>Reconfigurable State-of-the-Art High Speed Data Processing Capabilities </li></ul>MAPLD 2009 Gordonicus LLC STS125 Mission No blind and buried vias Flight Board meets NASA and IPC 6012 class 3 standards <ul><li>1553 </li></ul><ul><li>100 Mb Ethernet </li></ul><ul><li>200 Mb Spacewire routers </li></ul><ul><li>COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2 </li></ul>This hardware platform provides these needs by combining: <ul><li>A Rad Hard LEON3FT Processor </li></ul><ul><li>1 Gbyte protected SDRAM </li></ul>Aeroflex LEON3FT UT699
  4. 4. LEON3FT Processing Applications <ul><li>Guidance, Navigation and Control (GNC) </li></ul><ul><li>Control and Data Handling (CDH) </li></ul><ul><li>Xilinx Monitoring and Reconfiguration </li></ul>MAPLD 2009 Gordonicus LLC
  5. 5. Xilinx Processing Applications <ul><li>High Speed DSP Algorithm Processing </li></ul><ul><li>Image Processing </li></ul><ul><li>Pose Estimation Algorithms </li></ul><ul><li>Communications / Radio </li></ul><ul><li>Data Encryption / Decryption </li></ul><ul><li>Waveform Processing </li></ul><ul><li>Instrument Data Validation and Compression </li></ul><ul><li>Application Reconfigurable While in Flight </li></ul>MAPLD 2009 Gordonicus LLC
  6. 6. SPECIFICATIONS <ul><li>5 PROCESSORS </li></ul><ul><li>LEON3FT ASIC </li></ul><ul><li>AeroFlex UT699 SPARC TM V8/LEON 3FT </li></ul><ul><li>66 MHz Up to 52.8 MIPS </li></ul><ul><li>Floating Point and MMU </li></ul><ul><li>TID: 300 krad (Si) </li></ul><ul><li>SEL Immune >110 MeV-cm2/mg </li></ul><ul><li>4 x 350 MHz PowerPC™ 405 </li></ul><ul><li>Heritage Implementation </li></ul><ul><li>Dual Xilinx QV4 FX60 </li></ul><ul><li>32 bit RISC processors </li></ul><ul><li>700+ DMIPS </li></ul><ul><li>TID: 250 krad (Si) </li></ul><ul><li>SEL Immune >110 MeV-cm2/mg </li></ul><ul><li>SEFI: 1.5E-6 Upsets/device/day (GEO) </li></ul><ul><li>STANDARD I/O INTERFACES </li></ul><ul><li>10 SPACEWIRE PORTS </li></ul><ul><li>Up to 200Mbps (Configurable) </li></ul><ul><li>Supports Cross stapping </li></ul><ul><li>Multiple configurations </li></ul><ul><li>CompactPCI </li></ul><ul><li>32 Bit, 33MHz </li></ul><ul><li>Master and Slave Mode Supported </li></ul><ul><li>PCI 2.2 Compliant </li></ul><ul><li>NASA Hypertronics connectors </li></ul><ul><li>Mil-Std-1553 A/B </li></ul><ul><li>Mil-Std-1553 BC/RT/MT </li></ul><ul><li>Based on the Actel Core1553 IP </li></ul><ul><li>CONSOLE PORT </li></ul><ul><li>LEON3FT UART </li></ul><ul><li>Rate configurable </li></ul>MAPLD 2009 Gordonicus LLC <ul><li>FRONT PANEL DEVELOPMENT / DEBUG PORTS </li></ul><ul><li>DEVELOPMENT </li></ul><ul><li>LEON3FT 10T/100 Ethernet port </li></ul><ul><li>Xilinx 10T/100 Ethernet port </li></ul><ul><li>DEBUG </li></ul><ul><li>LEON Debug Serial Port </li></ul><ul><li>RTAX Debug Serial Port </li></ul><ul><li>Xilinx Debug Serial Port </li></ul><ul><li>JTAG </li></ul><ul><li>MEMORY </li></ul><ul><li>1 GByte SDRAM </li></ul><ul><li>Reed Solomon Protected corrects for 2 nibble upsets </li></ul><ul><li>8 GByte FLASH </li></ul><ul><li>stored in two banks </li></ul><ul><li>16 Gbit SDRAM </li></ul><ul><li>4Gbits per PPC405 </li></ul><ul><li>2 MBbyte SRAM </li></ul><ul><li>Protected (Self Scrubbing) </li></ul><ul><li>32 KByte PROM </li></ul><ul><li>CONFIGURABLE I/O </li></ul><ul><li>10 RS422/LVDS Transmit Ports </li></ul><ul><li>Xilinx configured (Quad redundant) </li></ul><ul><li>10 RS422/LVDS Receive Ports </li></ul><ul><li>Xilinx configured (Quad redundant) </li></ul><ul><li>39 Xilinx Backplane I/O </li></ul><ul><li>12 Actel I/O </li></ul><ul><li>2 LEON GPIO </li></ul><ul><li>2 Backplane Spacewire </li></ul><ul><li>Backplane Ethernet </li></ul><ul><li>SMALL SIZE </li></ul><ul><li>DIMENSIONS </li></ul><ul><li>Standard 3U cPCI </li></ul><ul><li>Single slot front panel configuration supports: 4 SpaceWire, 1553 A/B , Console port and Debug. </li></ul><ul><li>Dual slot front panel configuration supports additional SpaceWire ports. </li></ul><ul><li>LOW POWER </li></ul><ul><li>LEON3FT </li></ul><ul><li>2.5Volt Core </li></ul><ul><li>Xilinx </li></ul><ul><li>1.2Volt Core </li></ul>
  7. 7. LEON3FT PROCESSOR & MEMORY <ul><li>LEON 3FT </li></ul><ul><li>AeroFlex UT699 </li></ul><ul><li>SPARC TM V8 </li></ul><ul><li>66 MHz Up to 52.8 MIPS </li></ul><ul><li>Floating Point and MMU </li></ul><ul><li>TID: 300 krad (Si) </li></ul><ul><li>SEL Immune >110 MeV-cm2/mg </li></ul>MAPLD 2009 Gordonicus LLC <ul><li>MEMORY </li></ul><ul><li>1GByte SDRAM </li></ul><ul><li>Reed Solomon Protected corrects for 2 nibble upsets </li></ul><ul><li>8GByte FLASH </li></ul><ul><li>Stored in two banks </li></ul><ul><li>2MBbyte SRAM </li></ul><ul><li>Protected (Self Scrubbing) </li></ul><ul><li>32KByte PROM </li></ul>
  8. 8. MAPLD 2009 Gordonicus LLC LEON3FT PROCESSOR & MEMORY LEON3FT Aeroflex UT699 2MByte SRAM (Internal EDAC ) 32KB PROM 1GByte SDRAM (Reed Solomon) 4GByte FLASH Actel RTAX TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 52.8 MIPS 4GByte FLASH
  9. 9. Xilinx QV4 FX60 FPGAs & MEMORY <ul><li>Quad redundant or independent PPC processing </li></ul><ul><li>Mixed operating systems </li></ul><ul><li>Partial or Full reconfiguration </li></ul><ul><li>CONFIGURABLE LOGIC per FX60 </li></ul><ul><li>Logic Cells: 56,880 </li></ul><ul><li>Slices: 25,880 </li></ul><ul><li>Distributed RAM: 395kb </li></ul><ul><li>XtremeDSP Slices: 128 </li></ul><ul><li>Block RAM: 4,176Kb </li></ul>MAPLD 2009 Gordonicus LLC <ul><li>EMBEDDED PowerPC 405 </li></ul><ul><li>350 MHz operation </li></ul><ul><li>16 KB instruction cache </li></ul><ul><li>16 KB data cache </li></ul><ul><li>32 bit RISC processors </li></ul><ul><li>700+ DMIPS </li></ul><ul><li>TID: 250 krad (Si) </li></ul><ul><li>SEL Immune >110 MeV-cm2/mg </li></ul><ul><li>SEFI: 1.5E-6 Upsets/device/day (GEO) </li></ul><ul><li>MEMORY </li></ul><ul><li>16Gbit SDRAM </li></ul><ul><li>4Gbits per PPC405 </li></ul>
  10. 10. MAPLD 2009 Gordonicus LLC Xilinx QV4 FX60 PPC 405 PPC 405 Xilinx QV4 FX60 XILINX PPC405 PROCESSORS & MEMORY PPC 405 512MByte SDRAM 200Mbps SpaceWire(4) Dual Xilinx QV4 FX60 PPC 405 700 DMIPs TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) 512MByte SDRAM 512MByte SDRAM 512MByte SDRAM LEON3FT Aeroflex UT699 Based on Heritage Architecture Implementation
  11. 11. Xilinx DSP Processing Architecture MAPLD 2009 Gordonicus LLC PPC1 PPC3 PPC0 PPC2 <ul><li>4 Designs = </li></ul><ul><li>Quad Redundant or Single Strand </li></ul><ul><li>2 Designs = 1 Design per Xilinx </li></ul><ul><li>1 Design TMRed using both Xilinx </li></ul>Flexible Design Options : Node Interconnections
  12. 12. Xilinx Reconfiguration MAPLD 2009 Gordonicus LLC A Singe Node can be reconfigured with PPC1 PPC3 PPC0 PPC2 Bottom Xilinx QV4 FX60 Top Xilinx QV4 FX60 Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric. Control Logic SDRAM SelectMap <ul><li>PPC Operating system </li></ul><ul><li>PPC application code or </li></ul><ul><li>Xilinx fabric reconfiguration </li></ul>WITHOUT disruption to the other nodes FLASH
  13. 13. STANDARD INTERFACES <ul><li>CompactPCI </li></ul><ul><li>Console Port Async UART </li></ul><ul><li>1553 </li></ul><ul><li>SpaceWire </li></ul>MAPLD 2009 Gordonicus LLC
  14. 14. CompactPCI MIL-STD-1553 A/B LEON3FT Console Port MAPLD 2009 Gordonicus LLC
  15. 15. SpaceWire Ports MAPLD 2009 Gordonicus LLC LEON3FT SpW Router 5 Port SpW Router 5 Port RTAX 200Mbps Configurable 200/100/50 Mbps 200Mbps Front Panel Conn. Thru-hole Jumpers F R O N T P A N E L C P C I P 2 Xilinx 200Mbps 10 Front Panel 4 Backplane 2 Backplane via Jumpers 200Mbps Configurable
  16. 16. Configurable I/O <ul><li>What if my instrument interface is not SpaceWire? </li></ul><ul><li>What if I need a custom interface on the backplane? ie: I2C </li></ul><ul><li>What if I forgot to add a control line to a device? </li></ul>MAPLD 2009 Gordonicus LLC
  17. 17. 73 User Defined I/O MAPLD 2009 Gordonicus LLC LVDS OR RS422 LEON3FT F R O N T P A N E L C P C I P 2 Xilinx 39 User Defined I/O LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 Sync / Async Serial IF I2C 1 Wire Protocol 10 Bi-Dir User Defined I/O 2 GPIO ACTEL 12 User Defined I/O
  18. 18. Development & Debug Ports <ul><ul><li>LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) </li></ul></ul><ul><ul><li>Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) </li></ul></ul><ul><ul><li>LEON and Xilinx Ethernet ports can be connected </li></ul></ul><ul><ul><li>LEON Dedicated Debug Port (DSU) </li></ul></ul><ul><ul><li>Xilinx I/O to be used as serial ports </li></ul></ul><ul><ul><li>Xilinx JTAG </li></ul></ul><ul><ul><li>LEON JTAG </li></ul></ul><ul><ul><li>ACTEL JTAG </li></ul></ul><ul><li>All Debug / Development ports are accessible from the front panel. </li></ul><ul><li>Facilitates Hardware Reuse </li></ul><ul><li>GSE reconfiguration without opening the box </li></ul>MAPLD 2009 Gordonicus LLC
  19. 19. RTAX 2000 CONFIGURATIONS <ul><li>CG624 Package Supports ALDEC RTAX development Suite. </li></ul><ul><li>Flexible architecture using Gaisler/Aeroflex Cores </li></ul>MAPLD 2009 Gordonicus LLC
  20. 20. MAPLD 2009 Gordonicus LLC
  21. 21. 512MB 512MB 512MB MAPLD 2009 Gordonicus LLC Application RTAX SpW Router DownLink0 512MB SpaceWire SpaceWire SpW Router DownLink1 MissionCrd0 MissionCrd1 MissionCrd2 MissionCrd3 PPC 405 uP PPC 405 uP PPC 405 uP LEON3FT PPC 405 uP
  22. 22. Availability <ul><li>Contact Aeroflex Colorado Springs </li></ul>MAPLD 2009 Gordonicus LLC
  23. 23. Future …. MAPLD 2009 Gordonicus LLC Xilinx SIRF V5 Xilinx SIRF V5
  24. 24. Next Effort MAPLD 2009 Gordonicus LLC LEON3FT 16 MBytes EEPROM 8 Port SpW Router 16 GBytes FLASH 1 GByte SDRAM 1553 3U cPCI
  25. 25. Gordonicus LLC www.gordonicus.com <ul><li>Hardware </li></ul><ul><ul><li>Gordon Seagrave </li></ul></ul><ul><ul><li>[email_address] </li></ul></ul><ul><ul><li>Dorian Seagrave </li></ul></ul><ul><ul><li>[email_address] </li></ul></ul><ul><li>Software </li></ul><ul><ul><li>Peter Cavender </li></ul></ul><ul><ul><li>[email_address] </li></ul></ul><ul><ul><li>John Gemmill </li></ul></ul><ul><ul><li>[email_address] </li></ul></ul>MAPLD 2009 Gordonicus LLC

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