CSU ID# 830147760
Hardware/Software Design of
Silicon Photonics and Photonic NoCs: A
Why photonic interconnects instead of metallic interconnects for intra-chip data
Metallic interconnects have RC-delays which increase with increase in frequency.
Slow data transfer rates which do not match with the current processing speed of the processing units on a chip.
Increase the overall FLOPS of the system.
How did the idea of silicon photonics began?
First paper published in 1984 by Goodman et al.
Photonics is being used for inter-chip communication and optical fibres are used widely for data transfer
Now, it is possible to fabricate optical waveguides on silicon chips easily
What things will be affected if photonic interconnects have to replace metallic ones?
Entire or part of metallic NoCs will be replaced by photonic NoCs.
Router structure, architectures, simulation tools will change
In this survey, I have highlighted few works on routers for photonic interconnects, NoC architectures based
on photonic interconnects and simulation tools which have been proposed to be used for simulation of
these architectures and techniques for improvement in power, latency and bandwidth with minimizing
Assaf et al. proposed an architecture in 2006 for
Two layered structure :
– Photonic interconnection network
– Electronic control network
Photonic router (fig)
PSE- photonic switching element
Deflection routing algorithm for contention
Failed because packets need they need alternate
path and so they set constraint on network
Brief power analysis was carried out but many
4x4 router by Assaf et al.
Photonic switching elements
Modulators based on microring resonators fabricated in silicon
Switching time – 30ps
5um ring radius
Power consumption <0.5mW when on, 1pJ to switch, negligible when
Low insertion loss
Modulating several wavelenghts at tens of Gb/s
In this architecture, torus topology augmented with gateway access
to facilitate injection and ejection without interference with the through
traffic on the torus, and
to avoid blocking between injected and ejected traffic.
3 types of switches in each GAP: (fig)
(1) a gateway switch is directly connected to the gateway in the
(2) injection switches are located on the torus rows; and
(3) ejection switches are located on the torus columns.
Each injected message travels from the gateway switch to an injection
switch. It then travels on the network to the ejection
switch associated with its destination core from which it is sent to the
gateway switch and out of the network. The design of the GAPs and the
traffic rules is used to avoid message blocking in them
Figure: Layout of a 16node 2D folded torus with 2_ path overprovisioning. Solid (dashed)
lines represent bidirectional (unidirectional) links. Network switches (squares) are shown in
dark gray, and the GAPs, made of gateways (circles), gateway switches (squares), injection
switches (triangles), and ejection switches (diamonds), appear in light gray. The GAP for one
node is emphasized.
Figure: 3 types of switches in each GAP
Assaf et al. performed power analysis to compare their
photonic NoC with electronic NoC
CMP 36 processing cores
800Gb/s peak bandwidth
512Gb/s average bandwidth
Uniform traffic model
XY dimension order routing
Calculated average power 3.2W
Better than metallic NoC
Figure reference: Assaf Shacham, Keren Bergman, Luca P. Carloni, “the Case for Low-Power Photonic Networks on Chip”, DAC 2007, June 4-8,
2007, San Diego, California, USA.
In 2009, S. Bahirat and S. Pasricha proposed a hybrid photonic architecture with a
clear comparison with the metallic NoC architecture
They compared the latency, throughput and power of electrical mesh, electrical
torus and their hybrid photonic for a defined number of nodes (4x4, 8x8 and 10x10
NoCs). As shown in fig. 5 for a 10x10 NoC, hybrid photonic NoC works the best in
terms of latency, throughput and power
torus for a
10x10 NoC (a)
Figure: 3D implementation of the proposed hybrid photonic
NoC -mesh of cores on the bottom layer, photonic
waveguide on the top layer
Figures Reference: Shirish Bahirat, Sudeep Pasricha, “Exploring Hybrid Photonic Networks-OnChip for Emerging Chip Multiprocessors”CODES+ISSS’09, October 11-16, 2009, Grenoble,
In 2009, Christopher et al. came up with a paper in which they showed
the implementation of photonic interface for core to DRAM
communication. They proposed a local mesh to global switches (LMGS)
topology They showed that ultimately, photonics enables almost an
order of magnitude improvement in throughput at similar latency and
In 2013, S. Bartolini et al. proposed an all-optical photonic network for
low power applications (Fig.) called Olympic.
Similarly, Y. Demir et al. proposed an architecture named Galaxy in
2013. This is a multi-chip architecture which builds a many-core “virtual
chip” by connecting multiple smaller chiplets through optical fibers.
Galaxy is designed to push back the power constraints, in addition to
overcoming the area and bandwidth limitations, while matching the high
performance of tightly-coupled chips. They successfully demonstrate that
Galaxy achieves 1.8-3.4x average speedup over competing single-chip
designs, and achieves 2.6x lower energy-delay product (6.8x maximum).
The careful design of optical paths in Galaxy minimize coupler crossings
and allows it to scale beyond 4K cores, showing significant promise as the
foundation of practical large-scale virtual chip designs. Finally, we show
that a scaled-out Galaxy attains significant speedup and energy efficiency
advantages over competing designs such as the Oracle Macrochip as it
achieves at least 2.5x speedup with 6x more power-efficient optical links
Figure: Configuration Architecture of Olympic:
low power all-photonic NoC
Figure Reference: Sandro Bartolin, Luca Lusnig and Enrico Martinelli, “Olympic: a Hierachical All-optic Photonic Network for Low-power Chip
Multiprocessors”, 16th, Euromicro Conference on Digital System Design, 2013
•N. Sherwood-Droz et al. proposed a work showing spatially non-blocking 4x4
•Dynamically switched using thermo-optically tuned silicon microring resonators
•wavelength shift to power ratio of 0.25nm/mW
•can route four optical input to four outputs with individual bandwidths of up to 38.5
•This work shows that the bridge between photonic NoCs and silicon is getting smaller
and smaller and gives a detailed description of algorithm, design and fabrication as
well as testing of these routers which are 4x4 and more of these can be used to extend
to bigger chips
•principle of operation is to use two microring resonators on the opposite sides of a
waveguide intersection so that both signals can be routed to both ways simultaneously
•wavelength of resonator is a function of temperature
• In 2009, Andrew Poon et al.
proposed a 5x5 microring resonator
based optical switch in their paper.
But the emphasis was on on
improvement of 4x4 router.. They
used various type of available
microring resonators to combine
them into a 5x5 router for photonic
Figure: Shown in color are four paths highlighting an
arbitrary configuration using the maximum number
Figure : (a) Schematic of a 5 _ 5 matrix switch comprising 20 identical microring
resonator-based switch elements coupled to aMMI crossing grid array with 25 crossings.
The dashed arrows illustrate some of the possible light paths connecting 5 different
input-ports (Iwest, Ieast, injection, Inorth, and Isouth) to five different output-ports
(Owest, Oeast, ejection, Onorth, and Osouth). (b) Physical layout of our proposed 5 _ 5
photonic matrix switch comprising 20 identical silicon microring resonator-based switch
elements coupled to aMMI crossing grid array with 26 crossings. The pink arrow depicts
one of the longest links (injection-to-east). The blue arrow depicts one of the shortest
links (west-to-ejection). An additional MMI crossing is employed at the intersection
between Isouth- and Oeast-ports. Black solid dots represent termination at the unused
•In 2012, Rui Min et al. proposed a N-port non blocking router uring microring
resonators. They showed that the N-port router performs better than the
previous routers cascaded to N-ports
•Xianfang Tan et al. proposed a low area-footprint microring resonator based
photonic router in 2012. This router had less area footprint and power than
previous types of routers as shown in fig. 10 above. But there was power loss that
is weakening of the optical signal to some extent which was calculated and shown
in this work.
Rui Min, Ruiquiang Ji, Qiaoshan Chen, Lei Zhang and Lin Yang, “A Universal Method
for Constructing N-Port Nonblocking Optical Router for Photonic Networks-On-Chip”,
November 15, 2012, IEEE.
Xianfang Tan, Mei Yang, Lei Zhang, Yingtao Jiang and Jianyi Yang, “A Generic Optical
Router Design for Photonic Network-on-Chips”, JOURNAL OF LIGHTWAVE
TECHNOLOGY, VOL. 30, NO. 3, FEBRUARY 1, 2012
Fig. 10. Connections between the add points and the
drop points of N-port nonblocking optical router
Power loss estimation of different size routers
compared to GWOR
Chen Sun et al. have presented a very prominent work in 2012 which gives information about the limitation of the extent till which we can
rely on software tools to calculate operation characteristics of optical NoCs as compared to electrical NoCs. Also DSENT is the first tool that
is able to capture the interactions at electronic/photonic interface and their implications on a photonic NoC
Figure Reference: Chen Sun et al., “DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip
Modeling”, 2012, IEEE
Photonic network technology, once relegated exclusively to large-scale telecommunication networks, has
in recent years gradually been penetrating into smaller scale networking domains, with the potential to
eventually become a viable architectural solution for on-board and chip-scale systems.
We have introduced PHOENIXSIM as a simulation environment for the design, analysis, and optimization
of these high-performance interconnection networks in a manner that accurately captures the physicallayer aspects of the devices while enabling system performance evaluation.
This combination of models and tools in a single integrated environment provides a unique resource for
the design exploration of the new systems enabled by photonic networks PhoenixSim then was the result
of recent work in photonics modeling, improving the architectural visibility concerning the trade-offs of
PhoenixSim provided parameterized models for photonic devices.
However, PhoenixSim lacked electrical models, relying instead on Orion for all electrical routers and links.
As a result, PhoenixSim used fixed numbers for energy estimations for electrical interface circuitry, such as
modulator drivers, receivers, and thermal tuning, losing many of the interesting dynamics when transistor
technology, data-rate, and tuning scenarios vary.
PhoenixSim in particular could not capture trade-offs among photonic device and driver/receiver
specifications that results in an area or power optimal configuration.
A survey of the important researches on the use of photonics for System-On-Chips has been
While most of the works done until now suggest that the use of photonics NoCs for on-chip
data transfer is beneficial, some works suggest that it is not so.
We have also seen many novel architectures which are entirely photonic NoCs or hybrid
photonic NoCs with some metallic components.
The increase in number of GFLOPS of processors due to photonic NoCs is evident based on
software simulation results.
We have also seen the best of the routing techniques suggested for routing data in form of
light signals through photonic NoCs.
Use of photonics for multi-core system-on-chips cannot be yet considered as a practically
viable option as the tools for design synthesis and fabrication of opto-electronic components
have not yet been developed completely as we saw earlier that the simulators had some
drawbacks of their own and.
Hence, it can be concluded that the potential power, bandwidth and latency difference
between photonics-based NoCs and their electronic counterparts is immense and with the
perfection in technology for the simulation and fabrication of photonic components on
silicon fabric, the on-chip realm is going to see a revolution.