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Multi-threading
your way out
Rokas Antanas Balevičius
Why we have “race conditions” ?
RAM L3 L2
L1 RAX
L1 RAX
Out-of-order execution
public void Thread1
{
a = 1;
b = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Assert(a == 1);
}
public void Thread1
{
b = 1;
a = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Assert(a == 1);
}
Compiler and JIT optimizations
var b = 0;
public void Thread1
{
b = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Foo();
}
var b = 0;
public void Thread1
{
b = 1;
}
public void Thread2
{
if (b == 0)
{
while(true) { continue; }
}
Foo();
}
Preemption
T1 T2 T3 TN
20 ms 20 ms 20 ms 20 ms
Limit Compiler and Jit optimizations
Limit CPU optimizations
Do things atomically
Part1: Memory barriers
“I Think”
- LinusTorvalds
“In practice, however, they are informal
prose documents”
- Smart people at Cambridge University
L1
CPU1
Bus
L1
CPU2
Everything goes through Cache
Reads are simple and pull based
L1
CPU1
Bus
L1 (A)
CPU2
L1 (A)
CPU1
Bus
L1 (A)
CPU2
Writes are exclusive
Modern cache is write-back
Cache is coherent (MESI)
L1 (A)
CPU1
Bus
L1 (A)
CPU2
L1 (A)
CPU1 (A+)
Bus
L1 (A)
CPU2
L1 (A+)
CPU1
Bus
L1 (A)
CPU2
L1 (A+)
CPU1
Bus
L1 (A+)
CPU2
Everything goes through Cache
Reads are pull based
Writes are exclusive
Cache is coherent (MESI)
Problem: idle on writes
Lets improve performance
public void Thread1
{
a = 1;
b = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Assert(a == 1);
}
L1 (B, A)
CPU1
Bus
Store
Buffer
L1 (A)
CPU2
Store
Buffer
L1 (B, A)
CPU1
Bus
Store
Buffer (A+)
L1 (A)
CPU2
Store
Buffer
L1 (B+, A)
CPU1
Bus
Store
Buffer (A+)
L1 (A)
CPU2
Store
Buffer
L1 (B+, A)
CPU1
Bus
Store
Buffer (A+)
L1 (A, B+)
CPU2
Store
Buffer
Boom!
CPU2 saw writes in different order
CPU1 did everything in order
L1 (A+, B+)
CPU1
Bus
Store
Buffer
L1 (A+, B+)
CPU2
Store
Buffer
Write Memory Barrier
public void Thread1
{
a = 1;
Thread.MemoryBarrier() ;
b = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Assert(a == 1);
}
L1 (B, A)
CPU1
Bus
Store
Buffer (A+)
L1 (A)
CPU2
Store
Buffer
L1 (B, A)
CPU1
Bus
Store Buffer
(A+, B+)
L1 (A)
CPU2
Store
Buffer
L1 (A+, B)
CPU1
Bus
Store
Buffer (B+)
L1 (A)
CPU2
Store
Buffer
L1 (A+, B+)
CPU1
Bus
Store
Buffer
L1 (A, B+)
CPU2
Store
Buffer
L1 (A+, B+)
CPU1
Bus
Store
Buffer
L1 (A+, B+)
CPU2
Store
Buffer
Acknowledging invalidates is slow
Lets improve performance again
L1
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1
CPU2
Store
Buffer
Invalidate
Queue
L1 (A, B)
CPU1
Bus
Store Buffer
(A+, B+)
Invalidate
Queue
L1 (A)
CPU2
Store
Buffer
Invalidate
Queue
L1 (A, B)
CPU1
Bus
Store Buffer
(A+, B+)
Invalidate
Queue
L1 (A)
CPU2
Store
Buffer
Invalidate
Queue (A)
L1 (A+, B+)
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1 (A)
CPU2
Store
Buffer
Invalidate
Queue (A)
L1 (A+, B+)
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1 (A, B+)
CPU2
Store
Buffer
Invalidate
Queue (A)
Read Memory Barrier
public void Thread1
{
a = 1;
Thread.MemoryBarrier() ;
b = 1;
}
public void Thread2
{
while(b == 0) {continue;}
Thread.MemoryBarrier() ;
Assert(a == 1);
}
L1 (A+, B+)
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1 (A, B+)
CPU2
Store
Buffer
Invalidate
Queue (A)
L1 (A+, B+)
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1 (A, B+)
CPU2
Store
Buffer
Invalidate
Queue
L1 (A+, B+)
CPU1
Bus
Store
Buffer
Invalidate
Queue
L1 (A+, B+)
CPU2
Store
Buffer
Invalidate
Queue
Memory barriers also limit compiler and JIT
optimizations
Full Memory Barrier
OK OK
OK
OK
OK
OK
Memory Barrier
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
Memory Barrier
Memory Barrier
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
Memory Barrier
NO!
NO!NO!
NO!
Barrier pairing
Part 2: Atomic operation
LOCK CMPXCHG
int locker = 0;
Interlocked.CompareExchange(ref locker, 1, 0) == 0
Solves preemption
Time to get back to reality
C# Thread vs OS Thread
High level critical sections
OK OK
OK
OK
OK
OK
Atomic
Acquire Barrier
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
Atomic
Release Barrier
Atomic
Acquire Barrier
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
NO!
NO!Atomic
Release Barrier
Kind of ok
Kind of ok
Atomic
Acquire Barrier
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
Atomic
Release Barrier
Memory Barrier
Atomic
Memory Barrier
Memory Barrier
Atomic
Memory Barrier
C# Primitive
C# Primitive
Code Line 1
Code Line 2
Code Line 3
Code Line 1
Code Line 2
Code Line 1
Code Line 2
Spinning
Blocking
Non blocking algorithms
It is all about Speculations
Usage and problems
Multithread GC
More non-blocking algorithms
Signaling
IO bound scenarios
….
Thank you

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