Devanshu Shrivastava

12 Followers

* Top Level Partitioning and Integration (Top to Bottom/Bottom to Top Flow). * Floorplanning, CTS, Placement & Routing. * Power & IR Drop Analysis. * Physical Verification. * DFM Closure. * Static Timing, Xtalk Analysis. * Algorithm developments on Physical Design. * Mixed Signal Top Level Physical Integration. * Experienced on Application Specific Instruction-set Processors (ASIP). ---------------- Specialties: ---------------- * Physical Design Implementation. * SoC Integration. * Hands-on Experience on multiple nodes - 28nm, 40/45nm, 65nm, 90nm, 130nm. --------------------------------------- Presentations (Public Domain) ---------------------------------------

devanshu vlsi management pmc sierra physical design semiconductor nxp soc bangalore bangalore metro rfid mifare smart cards storage sas san networking talus icc magma cadence soc encounter synopsys atoptech bits pilani architecture philips hdtv ic asic license servers ic design project management semiconductors perl p&r ic physical design de bono google six hats technical resource technical management project management one minute management time management

Activity
About

Devanshu Shrivastava

Presentations

Whats Inside These Gadgets

Essence Of One Minute Management

Tips On Time Management

Six Thinking Hats Summary

Physical design relational_db_devanshu

HDTV Chip From NXP (PNX85500)

PM8056 Chip SAS Expander from PMC Sierra

MIFARE IC Soultion From NXP

Likes

44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick

HDTV Chip From NXP (PNX85500)

PM8056 Chip SAS Expander from PMC Sierra