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Gda ipsoc blr_hic_final

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Gda ipsoc blr_hic_final

  1. 1. Design Challenges & Trengs in High Speed Interconnect IPsRavi ThummarukudyL&T Infotech/GDA<br />Sept 2010<br />Confidential | Copyright © Larsen & Toubro Infotech Ltd.<br />
  2. 2. Agenda<br /><ul><li>Introduction and Background
  3. 3. Rationale for High Speed Serial Interconnects
  4. 4. Comparison of High Speed Connectivity
  5. 5. Challenges of IP adoption
  6. 6. Software IP
  7. 7. USB 3.0 Overview
  8. 8. Answer any questions on the above topics</li></li></ul><li>Top 100 innovative service providers,<br />2009<br />- Global Services<br />Company Overview<br /><ul><li>Global provider of comprehensive, end-to-end
  9. 9. software & hardware services & solutions</li></ul>Manufacturing – <br />Hi Tech Products<br />Insurance<br /><ul><li>15+ years of international experience
  10. 10. Presence : NA, APAC, Europe, Middle East, Africa
  11. 11. Company Strength: 11,000+; Revenue: US$ 432M</li></ul>Energy & Petrochemical<br /><ul><li>25 Fortune-100 customers</li></ul>Industry Presence<br />Banking & Financial Services<br /><ul><li>Amongst India’s Leading software companies
  12. 12. Wholly owned subsidiary of Larsen & Toubro Ltd.
  13. 13. 7 decade history in India as a premier engineering company
  14. 14. Revenues: US$ 9.8 Billion</li></ul>Manufacturing –<br />Packaged Goods<br />Product Engineering Services<br />Corporate Certifications<br />
  15. 15. Product Engineering Services<br />
  16. 16. Performance<br />Cost<br />Space<br />Power<br />INCREASE<br />REDUCTION<br />REDUCTION<br />REDUCTION<br />High Speed Interconnect Rationale<br /><ul><li>Cabling
  17. 17. PS >1Kwatt
  18. 18. Chip Cost
  19. 19. System Cost
  20. 20. Multi-Core CPU-GPU
  21. 21. Pins
  22. 22. Power Awareness
  23. 23. Application Awareness
  24. 24. Connectivity Requirements
  25. 25. Process Nodes
  26. 26. SiP
  27. 27. SOC
  28. 28. Integration & Bandwidth</li></li></ul><li>SOC versus SiP Tradeoffs<br />IP Cores<br />DFT Logic<br />Glue Logic<br />Processor <br />Cores<br />Bus Architecture<br />Memory<br />Embedded <br />Core<br />Communication & Interface<br /> Peripherals<br />Analog<br />Circuitry<br />
  29. 29. OCTEON II – Block Diagram<br />Source: Cavium Website<br />
  30. 30. Multicore Communications Processor SOC<br />Features:<br />PowerPC Processor<br /><ul><li> Up to Quad PowerPC 476 Cores</li></ul>Serial High-Speed Interfaces:<br /><ul><li>x1/x4 SRIO upto 3.125Gb/s
  31. 31. X2 10GbE (XAUI Based )
  32. 32. X1/x2/x4 PCIeupto 5Gb/s upto 3 ports</li></ul>Acceleration Engines:<br /><ul><li> Packet Processing (20Gb/s)
  33. 33. Security Engine (10Gb/S)
  34. 34. Traffic Manager/Scheduler ( upto 6levels of hierarchy )</li></ul>Applications:<br /><ul><li> 3G/4G Mobile Access Systems
  35. 35. eNodeB
  36. 36. Enterprise Gateways
  37. 37. Mobile Broadband RNC Applications</li></ul>Source: LSI Logic Website<br />
  38. 38. Next Gen Wireless Baseband Processor SOC<br />Source: Mind speed Website<br />
  39. 39. PCI Express Interconnect<br />
  40. 40. MIPI IPs<br />Camera<br />Tx<br />Display<br />Rx<br />DSI -1<br />CSI -2<br />Tx<br />Application<br />Processor SoC<br />Rx<br />Display<br />Rx<br />Co-Processor<br />SoC<br />Tx<br />Tx<br />D-PHY<br />D-PHY<br />DSI -2<br />Base Band<br />Processor SOC<br />MPHY<br />PA<br />RF<br />DIG RF<br />
  41. 41. USB – Super Speed Interconnect<br />Source: USB IF<br />
  42. 42. High Speed Interconnects – Comparison<br />PCIe 2.5 Gb/s – 8Gb/s<br />SRIO – Rev 1.3 supports 1.0Gbps; Rev 2.0 - 3.125Gbps, 5Gbps & 6.125Gbps<br />XAUI – 3.125Gbps – 6.125Gbps<br />USB 3.0 – 5Gbps<br />MULTI – PROTOCOL SERDES 1Gb/s – 10Gb/s – PHY’s<br />13<br />
  43. 43. Memberships<br />
  44. 44. IP Channels<br />ASIC/Design Service<br />Companies<br />IP Vendor<br />Silicon Vendors<br />OEM/ODM<br />IP<br />IP Integration Services <br />
  45. 45. HW Interconnect IP Portfolio<br />Hyper Transport<br />Cave<br />Tunnel<br />Host<br />Bridge<br />Switch Port<br />PCI Express*<br />Endpoint<br />Root Complex<br />Switch port/Switch <br />AMBA Bridge<br />Rapid IO*<br />Serial<br />Parallel<br />AXI Bridge<br />Processor*<br />IBM<br />Power PC 405<br />Power PC 460<br />Ethernet*<br />10/100/1G MAC<br />10G MAC<br />HiGig<br />DDR3/2 Controller<br />Interlaken<br />DP/HDMI<br />MIPI*<br />SPI 4.2*<br />Single channel<br />Multi channel<br />Security IPs<br />3DES, AES, MD5, RSA, SHA2, HDCP, BISS-E<br />USB3.0<br />Device<br />Host<br />Hub<br />GPON<br />OLT MAC<br />
  46. 46. IP Portfolio<br />AMBA 3 AXI & AMBA 2.0 AHB<br />HDMI<br />Controller<br />Memory <br />DDR3/2 CTRL<br />Power PC<br />ARM<br />IPMI<br />Display Port Controller<br />DLNA<br />LTE- UE<br />USB 2.0/3.0<br />Host, Hub<br />Device<br />X86<br />DSP<br />MIPS<br />DVB-H<br />TRO69<br />SoftwareIP<br />PCIe Gen1/2/3 <br />Controller<br />HT<br />SRIO<br />Ethernet<br />MIPI/UNIPRO<br />HW IP<br />
  47. 47. INTERCONNECT APPLICATIONS<br />
  48. 48. HW IP Reference Platforms<br />PCIe Platform<br />DDR Memory Platform<br />Market Leader in <br />Interconnect IP<br />Reference Platforms<br />USB 3.0 Platform<br />10-GbE Platform<br />MIPI Platform<br />
  49. 49. Integration<br />Quality<br />Verification<br />Qualifying IP<br />Cost<br />Lack of Stds<br />Timing<br />Reuse<br />Vendor Relation<br />0%<br />5%<br />10%<br />15%<br />20%<br />25%<br />30%<br />IP Adoption Challenges<br />Top 3 Issues<br /> Source: Gartner<br />Percentage of Survey Respondents<br />
  50. 50. Confidential | Copyright © Larsen & Toubro Infotech Ltd.<br />21<br />
  51. 51. LTE UE Stack<br /><ul><li>Compliance to latest 3GPP Release 8 Specification for MAC, RLC, RRC, PDCP and NAS Layer implementation
  52. 52. FDD Mode operation
  53. 53. PHY and OS agnostic protocol stack
  54. 54. Protocol abstraction for allowing inter-operability with 3rd party applications
  55. 55. APIs for MAC-PHY interface</li></ul>Commercial Grade UE stack compliant to 3GPP Rel.8 March’09 specs<br />22<br />
  56. 56. DVB-H Client<br />DVB-H<br />Broadcast Network<br />Broadcast Server<br />Content<br />Users<br />Overview<br /><ul><li>L&T Infotech’s DVB-H Component fulfill core software functions as part of the DVB-H middleware
  57. 57. This components is completely modular in architecture and ANSI C compliant
  58. 58. Support for JSR 272
  59. 59. This component can be easily portable to various OS
  60. 60. Windows Mobile, Symbian
  61. 61. Customizable to be integrated with 3rd party components</li></ul>Features<br /><ul><li>FLUTE
  62. 62. PSI/SI
  63. 63. ESG Engine
  64. 64. OS Abstraction Layer
  65. 65. Receiver Abstraction Layer for tuner abstraction
  66. 66. Integration Layers for XML, Media Player and Zip
  67. 67. Application APIs
  68. 68. OMA-BCAST and IPDC support
  69. 69. IPv4 and IPv6 support </li></ul>.<br />
  70. 70. TR-069 Component Technical Details<br />Features<br />Technical Specification<br /><br /><ul><li> Auto Configuration of CPE at initial connection
  71. 71. ACS initiated dynamic provisioning of CPE
  72. 72. Diagnostics information reporting from CPE and diagnostic test
  73. 73. Web identity management for customizing web content
  74. 74. Configurable transport level security
  75. 75. Authentication with shared secrets and MD5 Digest
  76. 76. Platform independent – integration layers
  77. 77. APIs and Parameter Mapping for device specific integration
  78. 78. Vendor specific parameter support
  79. 79. Data Models support - IGD, STB, VoIP, NAS, PON devices
  80. 80. TR-069 CWMP v1.1 Amendment 2
  81. 81. TR-111 LAN device management
  82. 82. HTTP v1.1
  83. 83. SSL 3.0 / TLS 1.0
  84. 84. SOAP v1.1 (Using GSOAP v2.7.10)
  85. 85. Linux kernel v2.6
  86. 86. Supported Data Models:
  87. 87. TR-098, TR-106 (IGD)
  88. 88. TR-104, TR-110 (VoIP)
  89. 89. TR-135 (STB)
  90. 90. TR-140 (NAS)
  91. 91. TR-142 (PON)</li></ul>Confidential | Copyright © Larsen & Toubro Infotech Ltd.<br />24<br />
  92. 92. USB 3.0 (Super Speed)<br />25<br />
  93. 93. USB 3.0 (Super Speed USB)<br /><ul><li>Increase the USB speed by 10X (5Gb/Sec)
  94. 94. Backwards compatible to USB 2.0
  95. 95. Almost 2X more power over cable
  96. 96. Similar connector foot print
  97. 97. New power management features
  98. 98. Newer transfer modes</li></li></ul><li>Need for Super Speed USB<br /><ul><li>Address the need for higher data rates for Disk drives, Flash Storage, Blu-ray , HD DVD etc
  99. 99. Newer applications demanding faster connectivity between PC and peripherals
  100. 100. HD Video applications in Net books, Portable Media Players, Mobile phones etc
  101. 101. Better energy efficiency overall
  102. 102. Stay ahead of competing technologies
  103. 103. USB 3.0 effort was started in 2007 and the initial deployment started in 2009; Technology is now ready for industry deployment.</li></li></ul><li>USB 3.0 expected Ramp<br />Source<br />www.ptgrey.com<br />
  104. 104. USB 2.0 vs. USB 3.0<br />
  105. 105. USB3.0 Design Challenges<br />Integration of Design IP, VIP and SW Stack<br />Legacy Integration<br />Verification and Validation<br />Compliance and Interoperability<br />Performance, Latency<br />Low Power<br />Software Support<br />
  106. 106. Pravega USB3 Device/Host Solution<br />PBUS/APB Interface<br />Application Interface<br />ROM Interface<br />DMA/xHCI<br />EP0 <br />Processor<br />Application Layer<br />Pravega SuperSpeed Core<br />USB2.0<br />Controller<br />(Optional)<br />PRX<br />PTX<br />PCTL<br />Protocol Layer<br />Speed Select<br />USB3 & USB2<br />Device<br />xHCI Host<br />Dual Mode<br />Hub<br />32 & 64 DP*<br />8/16/32 Bit PIPE<br />LRX<br />LCTL<br />LTX<br />Link<br />Layer<br />Receive<br />Control<br />Transmit<br />USB3 PIPE IF<br />UTMI /ULPIIF<br />PCS<br />USB2 PHY<br />PMA<br />USB2 IF<br />USB3 IF<br />
  107. 107. Confidential © L&T Infotech / GDA Technologies, Inc.<br />Pravega USB3 Hub Solution<br />PBUS Interface<br />ROM Interface<br />USB3 PIPE IF<br />Receive<br />Transmit<br />Control<br />LRX<br />LTX<br />LCTL<br />Link Layer<br />R<br />E<br />G<br />I<br />S<br />T<br />E<br />R<br />S<br />E<br />T<br />PRX<br />PCTL<br />PTX<br />Protocol<br />Layer<br />Pravega SuperSpeed DPN<br />Pravega SuperSpeed DP0<br />PRX<br />PTX<br />PRX<br />PTX<br />PCTL<br />PCTL<br />Pravega SuperSpeed UP<br />Protocol Layer<br />Protocol Layer<br />PNPI<br />USB3<br />Hub<br />32 & 64 DP*<br />8/16/32 Bit PIPE<br />Hub Core Matrix<br />Header Aggregator<br />EP0 Processor<br />Header Router <br />LRX<br />LCTL<br />LRX<br />LCTL<br />LTX<br />LTX<br />Link<br />Layer<br />Link<br />Layer<br />PNPI<br />Receive<br />Control<br />Transmit<br />Receive<br />Control<br />Transmit<br />PNPI<br />USB3 PIPE IF<br />USB3 PIPE IF<br />
  108. 108. Overcoming Adoption Challenges from Vendor side<br /><ul><li>Highly configurable solution to adapt to customer design
  109. 109. Provides huge options for Hardware and Software configurability
  110. 110. Verified against 3rd Party VIPs
  111. 111. Interoperated with USB3 PIPE Compliant PHYs
  112. 112. Passes Protocol Compliance tests (USB3CV)
  113. 113. In-House Validation platform for Device, Host and Hub functionality and Application Drivers
  114. 114. Collaboration with MCCI for Compliant USB 3.0SW Stack</li></li></ul><li>Pravega Device Controller Validation Setup<br />ONFI MSC <br />CTLR<br />Xilinx<br />FPGA<br />Pravega<br />Device <br />Controller<br />USBCV Test Suite<br />USB3 STD B<br />Connector<br />USB3 Cable<br />GDA IPVP Board<br />(Pravega Device Controller)<br />USB3 STD A<br />Connector<br />USBIF Host (NEC/Fresco) <br />Board<br />
  115. 115. GDA USB Validation Platform<br />Xilinx Virtex5-xcv110T-2 FPGA or xcv200T-2<br />One USB3 STD A Host Receptacle<br />One USB3 STD B Device Receptacle<br />USB PIPE Connector<br />On board micron ONFI Flash<br />One PCIe Edge Connector<br />One PCIe Slot Connector<br />
  116. 116. Pravega Device Controller Validation Setup<br />
  117. 117. Summary<br /><ul><li>Integrating high speed interconnect is a design necessity to increase performance, Reliability while reducing cost
  118. 118. There are many challenges in IP adoption and careful planning and verification is the key
  119. 119. Configurability , Compliance and inter operability are key requirements in selecting the right IP
  120. 120. Questions?</li>

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