How can we keep our FPGAs from falling into the Productivity Gap

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Phil Dworsky is a veteran of more than 25 years in EDA and IP. With Synopsys since 1993, he is currently director, strategic alliances as well as publisher of Synopsys Press, an imprint of Synopsys creating and delivering technical and business publications. Prior to his current positions, Phil held management positions in marketing, technical marketing and corporate applications at Synopsys, most recently as director, marketing and applications for DesignWare IP.

Phil was a co-founder and principal engineer at Performance Processors, a parallel processing company, and was also a co-founder of Silicon Solutions/Zycad, an early provider of simulation acceleration technology. He started his career at Hewlett-Packard as a hardware and software designer. Phil holds a Bachelor of Science degree with high honors in electrical engineering and computer science (EECS) from Princeton University.

www.design-reuse.com

Published in: Technology, Design
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How can we keep our FPGAs from falling into the Productivity Gap

  1. 1. How can we keep our FPGAs from falling into the Productivity Gap? Phil Dworsky Synopsys© Synopsys 2011 1
  2. 2. The view from 1997 . . .© Synopsys 2011 2
  3. 3. How did we survive? • The Productivity Gap didn’t happen – Well, not yet anyway • Why? – More IP, Bigger IP – Better Tools – R&D Investment© Synopsys 2011 3
  4. 4. ASIC/SoC design flow today (simplified) IP Specify Enter Verify Build Proto & Silicon Debug Debug© Synopsys 2011 4
  5. 5. FPGA Design In The Beginning Enter Proto & Debug© Synopsys 2011 5
  6. 6. FPGA Design Today (as it needs to be) NOTE: Embedded Software development and debug is a dominant effort in chip design. It is exactly the same for FPGA and ASIC/SoC. Specify Enter Verify Proto & Debug© Synopsys 2011 6
  7. 7. One More Thing . . . DesignWare IP Design RTL FPGA Synthesis SoC Implementation Certify/ DW Implementation Galaxy DW Implementation Synplify Premier Common IP and Source Code for FPGA, for Prototype, for ASIC/SoC© Synopsys 2011 7
  8. 8. The View in 2011 . . . • Front-end design for FPGAs is already as complex as it is for ASIC/SoC but some FPGA designers are still in denial • There will be an FPGA Productivity Gap • It can be solved . . . Should we expect the FPGA vendors to do this “for free?” – More IP, bigger IP Will FPGA designers (and verifiers) – Better Tools make the investment? – R&D Investment Will FPGA companies freely open access to third-party tool & IP vendors?© Synopsys 2011 8

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