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ECESLU Microprocessors lecture 2

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A lecture slide on computer languages and the Z-80 module as outlined from the book Microprocessors and MIcrocomputers by John Uffenbeck

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ECESLU Microprocessors lecture 2

  1. 1. Lecture 02 Computer Language and the Z-80 Module Microcomputers and Microprocessors By: John Uffenbeck ECE @Saint Louis University, Baguio City 1 Prepared by: Engr. Jeffrey Des B. Binwag
  2. 2. Computer Language • A computer language is a structured form of communication between a programmer and the microprocessor. • Computer Language Hierarchy: • High-level language. Made up of English like terms more suitable for human understanding. • Low-level Language • Assembly Level. Made up of Alphanumeric characters called Mnemonics. • Machine Level. Made up of Binary codes usually expressed in its shorthand Hexadecimal form. ECE @Saint Louis University, Baguio City 2
  3. 3. Language Translators • Assembler. A process or a program designed to convert assembly level language programs down to machine level. – Hand Assembly. Is the manual process of assembly making use of a look up table of one-to-one correspondence between a mnemonic and its equivalent machine level equivalent • Compiler. A process or a program designed to convert high level language programs down to machine level. ECE @Saint Louis University, Baguio City 3
  4. 4. Computer Architecture • Computer architecture defines the physical structure by which a microprocessor is built • COMPUTER ARCHITECTURES – Von Neuman Architecture. A three-bus architecture that makes use of an address bus, data bus, and control bus to interconnect the three main parts of a computer. – Harvard Architecture. A four-bus architecture that makes use of an address bus, data bus, control bus, and a separate bus for instructions to interconnect the three main parts of a computer. ECE @Saint Louis University, Baguio City 4
  5. 5. Von Neuman Architecture I/O Address Bus CPU Memory Control Bus Data Bus Address Bus Control Bus ECE @Saint Louis University, Baguio City 5
  6. 6. Harvard Architecture Instruction Bus Address Bus Address Bus CPU Memory I/O Control Bus Data Bus Control Bus ECE @Saint Louis University, Baguio City 6
  7. 7. The Z-80 Microporcessor • A 40-pin DIP chip developed by Zilog in 1974 • Von-Neuman Architecture • 16/8 bit address bus • 8 bit data bus • 4 pin control bus • Maximum clock frequency of 8 MHz ECE @Saint Louis University, Baguio City 7
  8. 8. Z-80 Pin Description ECE @Saint Louis University, Baguio City 8
  9. 9. Z-80 Programming Model A F B C D E H L B’ C’ D’ E’ H’ L’ ECE @Saint Louis University, Baguio City 9 PC IR SP A’ F’ IX IY 16 Bits
  10. 10. Z-80 Internal Registers • A-L. General Purpose Registers • A’-L’. Alternate Registers • A. Accumulator • F. Flag Register • PC. Program Counter • IR. Instruction Register • SP. Stack Pointer • IX-IY. Index Registers ECE @Saint Louis University, Baguio City 10
  11. 11. Z-80 Control Signals • MEMR. Memory Read • MEMW. Memory Write • IOR. Input Read • IOW. Output Write * Z-80 Control signals are not directly generated by the microprocessor. ECE @Saint Louis University, Baguio City 11
  12. 12. Z-80 Instruction Format OP-CODE OPERAND ECE @Saint Louis University, Baguio City 12 (END) • OP-CODE – Operation Code – The first byte of the instruction that defines its general intent. • OPERAND – Additional instruction bytes that provide instruction details whenever necessarry
  13. 13. Z-80 Instruction Groups • Every microprocessor has its own instruction set for programming. The following are the instruction groups under which instructions in the Z-80 instruction set are grouped: – Data Transfer – Arithmetic – Logical and Rotate – Branch – Stack, I/O, Machine Control – Exchange, Block Transfer, and Search – Bit Manipulation ECE @Saint Louis University, Baguio City 13 (END)
  14. 14. Z-80 Addressing Modes • Define the manner by which data is transferred from one location of the microcomputer system to another MODE EXAMPLE OPERATION DIRECT LD A, (1800) A  (1800) REGISTER LD A, B A  B REGISTER LD A, (HL) A  (1800) INDIRECT Ex. HL = 1800 IMMEDIATE LD A, 05 A  05 RELATIVE BRANCHING JP, (PC + 10) PC = PC + 10 INDEXED LD A, (IX) Ex. IX = 1800 A  (1800) ECE @Saint Louis University, Baguio City 14 (END)
  15. 15. Thank You ECE @Saint Louis University, Baguio City 15

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