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This paper presents a unified architecture design o
f the RSA cryptosystem i.e. RSA crypto
accelerator along with keypair generation. A struc
tural design methodology for the same is
proposed and implemented. The purpose is to design
a complete cryptosystem efficiently with
reduced hardware redundancy. Individual modular arc
hitectures of RSA, MillerRabin Test and
Extended Binary GCD algorithm are presented and the
n they are integrated. Standard
algorithm for RSA has been used. The RSA datapath h
as further been transformed into DPA
resistant design. The simulation and implementation
results using 180nm technology are shown
and prove the validity of the architecture.
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