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More Than MooreAntonio L. P. RotondaroCTI Renato Archer
R&D Total PersonnelPhDMSBSTechCentro de Tecnologia da Informação Renato ArcherFigures:– Total area = 320.000 m2– Built are...
Microelectronics Software ApplicationsR&D AreasHW and IC DesignMicrosystemsPackagingQualification ofElectronic Product...
Final CommercialProductDigital, Analog and RF0,18 µm Technology1st batch from FoundryEngineering PhaseTest on ProtoboardBa...
Main Tools:Mask Fabrication Wet benchMask aligner MJB3Magnetron sputtering Balzers BAS 450Optical profilemeter ZygoPa...
OpticalMicroscopeSEM w.EDX/WDSTeradyne MicroFlextesterWafer prober –Micromanipulator 6400Logic analyzer-HP16500BFIB/SEM du...
Burn-inClimatic chamber– Vötsch 7033SamplepreparationThermal cyclingchamber Vötsch7012Reliability and Certification Lab
IC Packaging GroupPrototypes;Components 01005;Printer, Pick&Place, Reflow;ProjectFailureAnalysisMulti ChipModules (MCM)SMT...
Available IC Packaging TechnologiesTechnologies Bump Deposition Stud Bump Wire Bonding Flip Chip Wafer Thinning Stac...
IC Packaging TechniquesWire BondingBGA assemblyChip-on-board Assembly
Customized Capsules and ConnectorsTechnologies Hermetic Sealing Metal/Ceramic Joint IR Sensors RFID MEMS & BioMEMS M...
Organic ElectronicsFlexible Solar CellsBulk-heterojuctionSolar CellsPET ITO PEDOT P3MET/CdSe QDAl/Ag
NanomaterialsNanostructures Fabricated by SputteringApplications:Electrodes; Sensors; Memories; Surface Functionalization
[1] R. R. Tummala,MOORES LAW MEETS ITSMATCH, IEEE Spectrum, p.44, June 2006.IC Packaging: More-than-Moore14
DSL CO Linecards19961st GenSingle Channel19982nd GenDual Ch19993rd GenDual Ch20004th GenQuad Ch20015th GenOctal Ch20026th ...
AR5BOMManufacturingProcessTechnology20005 chips740 discretesu CMOSu Analogu Flashu SDRAM2005 – AR53 chips415 discretesu CM...
IC Packaging: 3D SoP[1] R. R. Tummala, MOORES LAW MEETS ITS MATCH, IEEE Spectrum, p. 44, June 2006.17
IC Packaging: Mobile Requirements18• Decreasing Thickness• Decreasing Weight• Increasing Functionality• Increasing Complex...
1971 – First Microprocessor 40042.3x103 transistors, 108Khz, 10μm,pMOS, 12V, 0.3W, 4 Bits, 16DIP2006 – Dual-Core IntelItan...
IC Packaging: 3D Packaging• Achieves Packaging Efficiency greater than 1.020 J.U. Knickerbocker et al., ECTC2012, pg.1068 ...
5 years Goal: Chip EmbeddingTechnologies Multi Chip Module (MCM) Flip Chip Through Silicon Vias (TSV)
Conclusions• Packaging integration– RFID IC– Antenna– Energy Harvesting– Battery– Sensors• Flexible substrate– Organic Ele...
Antonio L. Pacheco RotondaroHead IC Packaging Divisionantonio.rotondaro@cti.gov.brTel.: +55 19 3746-6195 - Fax: +55 19 374...
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I International Workshop RFID and IoT - Dia 20 - More than Moore - Antonio Luis Pacheco Rotondaro - CTI

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More than Moore - Antonio Luis Pacheco Rotondaro - CTI

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I International Workshop RFID and IoT - Dia 20 - More than Moore - Antonio Luis Pacheco Rotondaro - CTI

  1. 1. More Than MooreAntonio L. P. RotondaroCTI Renato Archer
  2. 2. R&D Total PersonnelPhDMSBSTechCentro de Tecnologia da Informação Renato ArcherFigures:– Total area = 320.000 m2– Built area= 14.000 m2– Personnel = 6002010 Budget:– OGU: R$ 12M– Projects: R$ 22M– Total: R$ 34M
  3. 3. Microelectronics Software ApplicationsR&D AreasHW and IC DesignMicrosystemsPackagingQualification ofElectronic ProductsSurface Interactionand DisplaysSoftware Qualityand ProcessImprovementInformationSystem SecuritySoftwareDevelopmentRobotics andComputer VisionDecision SupportSystems3D TechnologiesMISSION: Create, apply and disseminate knowledge in Information Technology, inarticulation with other social and economic agents, promoting innovations according tosociety demands.
  4. 4. Final CommercialProductDigital, Analog and RF0,18 µm Technology1st batch from FoundryEngineering PhaseTest on ProtoboardBackend & Final TestsGeometrical DescriptionFunctional blocsSymbolic language descriptionSimulationDesign House
  5. 5. Main Tools:Mask Fabrication Wet benchMask aligner MJB3Magnetron sputtering Balzers BAS 450Optical profilemeter ZygoPattern Generator Heidelberg DWL66Clean rooms:400 m2, Class 1000 & 100 w. tunnel class 10Microfabrication and MicrosystemsInfrastructure
  6. 6. OpticalMicroscopeSEM w.EDX/WDSTeradyne MicroFlextesterWafer prober –Micromanipulator 6400Logic analyzer-HP16500BFIB/SEM dual beam (@UNICAMP)Characterization and Failure AnalysisFocused-Ion-Beam Scanning Electron Microscope
  7. 7. Burn-inClimatic chamber– Vötsch 7033SamplepreparationThermal cyclingchamber Vötsch7012Reliability and Certification Lab
  8. 8. IC Packaging GroupPrototypes;Components 01005;Printer, Pick&Place, Reflow;ProjectFailureAnalysisMulti ChipModules (MCM)SMTAsemblyPCB, Hybrid Circuits,Multi-Chip-Modules;Chip-on-board (COB);Wire Bonding of Au or Al;Custom Capsules;X-Ray & Ersascope;BGA & µBGA reballing;Wire-bonding;Alumina or Silicon substrates;3 Metal Levels;Embedded Components:Resistors, Capacitors e Inductors;
  9. 9. Available IC Packaging TechnologiesTechnologies Bump Deposition Stud Bump Wire Bonding Flip Chip Wafer Thinning Stacked Dies  IR Sensors RFID MEMS &BioMEMS MemoriesAplications
  10. 10. IC Packaging TechniquesWire BondingBGA assemblyChip-on-board Assembly
  11. 11. Customized Capsules and ConnectorsTechnologies Hermetic Sealing Metal/Ceramic Joint IR Sensors RFID MEMS & BioMEMS MemoriesAplications
  12. 12. Organic ElectronicsFlexible Solar CellsBulk-heterojuctionSolar CellsPET ITO PEDOT P3MET/CdSe QDAl/Ag
  13. 13. NanomaterialsNanostructures Fabricated by SputteringApplications:Electrodes; Sensors; Memories; Surface Functionalization
  14. 14. [1] R. R. Tummala,MOORES LAW MEETS ITSMATCH, IEEE Spectrum, p.44, June 2006.IC Packaging: More-than-Moore14
  15. 15. DSL CO Linecards19961st GenSingle Channel19982nd GenDual Ch19993rd GenDual Ch20004th GenQuad Ch20015th GenOctal Ch20026th GenOctal ChIC Packaging: SOC – Saving Space15
  16. 16. AR5BOMManufacturingProcessTechnology20005 chips740 discretesu CMOSu Analogu Flashu SDRAM2005 – AR53 chips415 discretesu CMOSu Analogu Flashu SDRAM1 chip<50 discretesu CMOSu Analogu Flashu SDRAMMemoryCommsProcessorDigitalPHYAnalogCodecLineDriverLineReceiver740DiscretesMemoryCommsProcessorDigitalPHY415DiscretesAFEMemory<50DiscretesSingle-ChipDSL ModemIC Packaging: SOC Integration16
  17. 17. IC Packaging: 3D SoP[1] R. R. Tummala, MOORES LAW MEETS ITS MATCH, IEEE Spectrum, p. 44, June 2006.17
  18. 18. IC Packaging: Mobile Requirements18• Decreasing Thickness• Decreasing Weight• Increasing Functionality• Increasing Complexity• Increasing I/O ports
  19. 19. 1971 – First Microprocessor 40042.3x103 transistors, 108Khz, 10μm,pMOS, 12V, 0.3W, 4 Bits, 16DIP2006 – Dual-Core IntelItanium “Montecito”1.7x109 transistors, 2GHz,65nm, CMOS, 1.2V, 130W,64 Bits, 775 Flipchip MCMIC Packaging: MCM Evolution19
  20. 20. IC Packaging: 3D Packaging• Achieves Packaging Efficiency greater than 1.020 J.U. Knickerbocker et al., ECTC2012, pg.1068 (2012)
  21. 21. 5 years Goal: Chip EmbeddingTechnologies Multi Chip Module (MCM) Flip Chip Through Silicon Vias (TSV)
  22. 22. Conclusions• Packaging integration– RFID IC– Antenna– Energy Harvesting– Battery– Sensors• Flexible substrate– Organic Electronics
  23. 23. Antonio L. Pacheco RotondaroHead IC Packaging Divisionantonio.rotondaro@cti.gov.brTel.: +55 19 3746-6195 - Fax: +55 19 3746-6028www.cti.gov.br

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