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C++ CoreHard Autumn 2018. Знай свое "железо": иерархия памяти - Александр Титов

Если вам важна скорость работы ваших программ, то вы обязаны понимать, как работает ваше "железо". Современный процессор -- это сложное устройство, многие механизмы которого могут неочевидным образом влиять на скорость исполнения вашего кода. В докладе дается обзорное представление основных структур современного процессора и подробно рассматривается работа иерархии памяти. Будут освещены следующие темы: организация кэш-памяти, принцип локальности, предподкачка данных, нежелательное общее владение данными, а также программные техники для эффективной работы с памятью.

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Know Your Hardware:
CPU Memory Hierarchy
Alexander Titov
About me
Alexander Titov
– CPU Hardware Architect
– 10 years of C++ experience (CPU simulation)
– Teaching Computer Architecture and Design
CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov
2
alexander.titov@atitov.com alexander-titov-cpu
How CPU Works?
CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov
3
Outside
World
Outside
Memory
CPU
How CPU Works?
CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov
4
1. Read instruction
2. Decode it
3. Read inputs
4. Execute instruction
5. Write result
1. Read next instruction
2. Decode it
3. Read inputs
CPU
Outside
Memory
Simplified CPU actions:what to do?010100…0101
a[0] = b[0]
+ 1?2a[0] =3
from MEM
from MEM
to MEM
what next?
Conclusion: CPU works a lot with Outside Memory
Is Outside Memory Fast?
CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov
5
CPU
Outside
Memory
CPU
Is Outside Memory Fast?
CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov
6
Outside
Memory
CPU
– No
~0.5 ns
4x~100 ns
Memory is very slow.
CPU would wait 99% of the time for Memory response.
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C++ CoreHard Autumn 2018. Знай свое "железо": иерархия памяти - Александр Титов

  • 1. + + + + + + + Know Your Hardware: CPU Memory Hierarchy Alexander Titov
  • 2. About me Alexander Titov – CPU Hardware Architect – 10 years of C++ experience (CPU simulation) – Teaching Computer Architecture and Design CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 2 alexander.titov@atitov.com alexander-titov-cpu
  • 3. How CPU Works? CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 3 Outside World Outside Memory CPU
  • 4. How CPU Works? CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 4 1. Read instruction 2. Decode it 3. Read inputs 4. Execute instruction 5. Write result 1. Read next instruction 2. Decode it 3. Read inputs CPU Outside Memory Simplified CPU actions:what to do?010100…0101 a[0] = b[0] + 1?2a[0] =3 from MEM from MEM to MEM what next? Conclusion: CPU works a lot with Outside Memory
  • 5. Is Outside Memory Fast? CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 5 CPU Outside Memory CPU
  • 6. Is Outside Memory Fast? CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 6 Outside Memory CPU – No ~0.5 ns 4x~100 ns Memory is very slow. CPU would wait 99% of the time for Memory response.
  • 7. Cache Hierarchy CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 7 Outside Memory CPU 10 GB – 1 TB 10 – 30 MB 256 KB – 1 MB 32 KB ~0.5 ns~100 ns ~3 ns ~10 ns ~30 ns Cache 3rd level Cache 2nd level Cache 1st level
  • 8. Cache Hierarchy In Action CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 8 Outside Memory CPU 10 GB – 1 TB 10 – 30 MB 256 KB – 1 MB 32 KB ~0.5 ns~100 ns ~3 ns ~10 ns ~30 ns missmissmiss
  • 9. Cache Hierarchy In Action CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 9 Outside Memory CPU 10 GB – 1 TB 10 – 30 MB 256 KB – 1 MB 32 KB ~0.5 ns~100 ns ~3 ns ~10 ns ~30 ns hit Locality principle: the same data is requested several times in a short period of time
  • 10. Experiment: Defining Cache Hierarchy CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 10 Intel(R) Xeon(R) Gold 6130 CPU, TDP 2.10GHz, Turbo 3.77Ghz 32 KB 1 MB 22 MB L1 Cache 32 KB L2 Cache 1MB L3 Cache 22MB Outside Memory 430 GB/s 128 B/cycle 170 GB/s 50 B/cycle 25 GB/s 7 B/cycle 13 GB/s 3 B/cycle
  • 11. Performance Optimizations • Rule #1: – Use tools: google benchmark, perf, Intel VTune Amplifier, etc. • Rule #2: Do educated decisions • Rule #3: Do not reinvent bicycle – For many tasks there are highly optimized libraries (e.g., Intel MKL) • Rule #4: Optimize in the following order – General algorithm (e.g., O(NlogN) vs. O(N^2)) – Memory allocation, copy vs. move, etc. – Data structures organization in memory and access patterns – Branches, code footprint – … CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 11 Measure it!
  • 12. Tip: Divide and Conquer • Split large workload in parts that fit in the cache CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 12 → improve locality cachesize Large workload Split workload
  • 13. Tip: Divide and Conquer • Split large workload in parts that fit in the cache CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 13 30x speedup Example: → 4096 parts x (16 KB x 1000 times)64 MB x 1000 times → improve locality cachesize Large workload Split workload
  • 14. Tip: Split Warm and Cold Data • All data transfers are performed in aligned chunks of 64 B (line) – Even if 1B is requested by instruction, the whole 64B chunk is read • If the rest of the line is not used, it occupies space and BW in vain CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 14 • Extract fields that are accessed more often (warm) into a separate object
  • 15. 0 64 128 Tip: Split Warm and Cold Data CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 15 struct Mixed { int warm; int cold[15]; }; Mixed mixed_array[N]; • Extract fields that are accessed more often (warm) into a separate object struct Warm { int warm; }; Warm warm_array[N]; Cold cold_array[N]; struct Cold { int cold[15]; }; 6% efficiency 100% efficiency • Decrease occupied cache space and memory bandwidth by 16x times! 0 64 128
  • 16. Tip: Dense Data Packing • By default, C++ has sparse data packing – Each field is aligned by its size (to prevent line splits) CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 16 struct Sparse { bool b0; int i; bool b1; double d; }; // 1B // 4B // 1B // 8B sizeof(Sparse) == ? struct _Sparse { bool b0; uint8_t padding0[3]; int i; bool b1; uint8_t padding0[7]; double d; }; b0 i b1 d #pragma pack(push) #pragma pack(1) struct Dense { bool b0; int i; bool b1; double d; }; #pragma pack(pop) sizeof(Dense) == struct LessSparse { bool b0; bool b1; int i; double d; }; sizeof(LessSparse) == b0 ib1 d b0 i b1 d 16 1424
  • 17. Pitfall: Split Atomic • Dense packing can be dangerous. E.g., lead to split line atomics. CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 17 #pragma pack(push) #pragma pack(1) struct alignas(64) SplitAtomic { uint8_t padding[63]; atomic<uint64_t> a; }; #pragma pack(pop) struct alignas(64) Atomic { uint8_t padding[63]; atomic<uint64_t> a; }; vs. • A split line atomic is ~300x slower that an usual atomic! 0 64 128 padding a atomic is in two lines 0 64 128 padding a
  • 18. Pitfall: False Line Sharing CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 18 Shared L3 Cache Core Core Core Core System Agent & Memory Controller want to write snoop snoopsnoopsnoop • Do not place independent data written by multiple threads into one line! – If data is only read → OK // each thread repeatedly writes // only its own element int thread_results[4]; • Example: • Core must “own” a whole line to be able to write it – The copies in the other Cores are removed Each write miss L1 and L2 caches! If the data were in different lines, it would be L1 hits 0 64
  • 19. What Next? • Docs: – Intel Architectures Optimization Reference Manual • Courses: – High-Performance Computing and Concurrency by Fedor G. Pikus • Tools: – Google Benchmark – godbolt.org / quick-bench.com – Intel VTune Amplifier CoreHard 2018. Know You Hardware: CPU Memory Hierarchy. Alexander Titov 19
  • 20. + + + + + + + Many thanks! Questions welcome :) alexander.titov@atitov.comAlexander Titov alexander-titov-cpu