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Track h tools for improving design productivity - altera


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Track h tools for improving design productivity - altera

  1. 1. Tools for Improving design productivity<br />Elhanan Sharon <br />Embedded Technology Specialist <br />ALTERA Department <br />
  2. 2. Agenda<br />FPGA Design challenges<br />Improving Productivity – What it Means?<br />Introduction to QSys – ALTERA System Integration tool<br />
  3. 3. System Design Challenges with FPGAs<br />Number of <br />system <br />components<br />in an FPGA<br /><ul><li>Increasing FPGA density
  4. 4. Growing FPGA I/O capabilities
  5. 5. FPGA becoming the heart of the system</li></ul>Time<br />Time spent on system integration<br /><ul><li>The time spent integratingeach additional componentincreases exponentially</li></ul>Number of system components in an FPGA<br />
  6. 6. Productivity Challenge for FPGA Designers<br />Spend significant amount of time on system integration <br />Core competency is innovation and product differentiation<br />System integration<br />Innovation<br />Product <br />differentiation<br />
  7. 7. Improving Productivity- What It Means ?<br />Do more with less—more complex products with same or less resources<br />Reuse across projects—avoid obsolescence<br />Reuse across locations<br />Lower risk—avoid “throw-away”<br />Reduce risk of design errors<br />Reduce risk of market changes<br />Reduce risk of schedule slips<br />Allow customers to focus on their value-added core competencies<br />
  8. 8. Tools to Improve Customer Productivity<br />As FPGAs move to the heart of the system, design software plays a key role in defining customer productivity<br />ALTERA Design Suite software tools leads the industry in several important areas<br />Compilation time<br />Timing analysis and Timing closure<br />Power optimization and Power closure <br />Team-based design methodology<br />System-level design tools<br />System Integration tools<br />
  9. 9. Introduction to Qsys:System Integration Made Easy<br />
  10. 10. Why Use System Integration Tools like Qsys?<br />Simplifies complex system development<br />Provides a standard platform supporting many IP cores<br />Enables design re-use<br />Raises the level of abstraction<br />Allows developers to focus on “value add” instead of glue logic and system interconnect<br />Scales easily to meet the needs of the end product<br />Reduces time to market<br />Reduces design development time<br />Less error-prone<br />Eases verification<br />
  11. 11. Qsys Foundation: SOPC Builder<br />SOPC Builder’s track record<br />Enjoyed ~10 years of success<br />Used by 10,000+ users worldwide<br /><ul><li>Trends in customer requirements:
  12. 12. Higher system bandwidth and increasing usage of high-performance IP cores
  13. 13. Growing system size requiring very scalable development tool
  14. 14. Shorter time to market and limited resources demanding a system re-use flow</li></li></ul><li>Qsys Raises the Level of Design Abstraction<br />Higher Abstraction and Improved Productivity Level<br />Low<br />Medium<br />High<br />System<br />Block<br />IP<br />System<br />Block<br />IP<br />System<br />Block<br />Block<br />IP<br />IP<br />System<br />System<br />Design Block Integration<br />IP Integration<br /><ul><li> Design a system with IP cores
  15. 15. IP re-use
  16. 16. IP verification</li></ul>SoC Integration<br /><ul><li> Design a system with systems
  17. 17. System re-use
  18. 18. System verification</li></ul>Schematic Entry Tool<br />SOPC Builder Tool<br />Qsys System Integration Tool<br />
  19. 19. Qsys: Moving To The Next Level<br />Based on Network-on-chip Architecture<br />High Performance Interconnect<br />Hierarchy<br />IP Management<br />Package as IP<br />Add toLibrary<br />(Design Reuse)<br />Design<br />System<br />Real-time System Debug<br /><ul><li>High performance interconnect
  20. 20. Hierarchy
  21. 21. Industry-standard interfaces
  22. 22. IP management capabilities
  23. 23. Real-time system debug</li></ul>SOPCBuilder<br />+<br />=<br />Industry-standard Interfaces<br />
  24. 24. Qsys Features<br />High performance: New interconnect based on network-on-chip architecture<br />Scalable systems: Hierarchical system design<br />Industry-standard interfaces: Connect IP cores of different interfaces together (Avalon, AXI, AHB, etc.)<br />Design re-use: IP management capabilities<br />Faster board bring-up: Real-time system debug<br />
  25. 25. Easy-to-Use System Integration UI<br />Library of<br />available IP<br />Connect IP and systems<br /><ul><li>Interface protocols
  26. 26. Memory
  27. 27. DSP
  28. 28. Embedded
  29. 29. Bridges
  30. 30. PLL
  31. 31. Your Systems</li></ul>IP 1<br />IP 2<br />IP 3<br />System 1<br />System 2<br />Design at a Higher Level of Abstraction by<br />Integrating IPs and Systems<br />
  32. 32. med<br />low<br />high<br />off<br />High Performance Interconnect<br />SOPC Builder<br />Qsys<br />Manual Pipelining<br />Manual Pipelining<br />System Interconnect Fabric<br />Higher Performance<br />QsysInterconnect<br />(Based on Network-on-chip <br />Architecture)<br />
  33. 33. <ul><li>SOPC Builder
  34. 34. Qsys</li></ul>High Efficiency Interconnect<br />25% Efficiency at Slave<br />Width Adaptor<br />Burst Adaptor<br />Master<br />Slave<br />32<br />128<br />Burst count = 8<br />Burst Count = 1<br />100% Efficiency at Slave<br />Width Adaptor<br />Burst Adaptor<br />Master<br />Slave<br />32<br />128<br />Burst Count = 8<br />Burst Count = 1<br />Bandwidth Available for Other Masters<br />Higher Efficiency = Higher Throughput<br />
  35. 35. Network-on-Chip (NoC) Architecture<br />Packet transactions and transport<br />Each command encapsulated in a packet to be sent to a slave<br />Each response encapsulated in a packet to be sent back to a master<br />Avalon-ST<br />Avalon-MM<br />Avalon-MM<br />Master<br />Network<br />Interface<br />Slave<br />Network<br />Interface<br />Avalon ST<br />Network<br />(Command)<br />Slave<br />Interface<br />Master<br />Interface<br />Master<br />Network<br />Interface<br />Avalon ST<br />Network<br />(Response)<br />Slave<br />Network<br />Interface<br />Slave<br />Interface<br />Master<br />Interface<br />Transport Layer <br />Transaction Layer <br />Transaction Layer <br />
  36. 36. Scalable System Design: Hierarchy<br />SOPC Builder<br />Qsys<br />Sub-system 1<br />Sub-system 2<br />Sub-system 3<br />Qsys advantage: hierarchy support<br /><ul><li> Fewer components = fast GUI
  37. 37. Fewer components = manageable
  38. 38. Enables system to scale</li></ul>Impacts on large systems: <br /><ul><li> GUI response
  39. 39. System management</li></li></ul><li>Industry-standard Interfaces<br />Mix industry-standard interfaces together<br />Master<br /> 1<br />Slave<br /> 1<br />AXI<br />OCP<br />Master<br /> 2<br />Slave<br /> 2<br />OCP<br />AXI<br />Master<br /> 3<br />Slave<br /> 3<br />Avalon<br />Avalon<br />Qsys Interconnect<br />P<br />P<br />P<br />P<br />P<br />P<br />A<br />A<br />A<br />A<br />A<br />A<br />C<br />C<br />C<br />C<br />C<br />C<br />K<br />K<br />K<br />K<br />K<br />K<br />E<br />E<br />E<br />E<br />E<br />E<br />AMBA<br />T<br />T<br />T<br />T<br />T<br />T<br />OCP<br />OC<br />Qsys: Avalon (10.1), AXI (2011)<br />
  40. 40. Design Re-use<br />Project A<br />Project B<br />Project C<br />Top<br />Top<br />Top<br />Qsys enables re-use of IP and systems with IP management capabilities<br />Top<br />Top<br />Add to Library<br />Package as IP<br /><ul><li>IP GUI wizard
  41. 41. System Top</li></ul>Qsys<br />
  42. 42. Faster Board Bring-up<br />Access the system in real time by sending read/write transactions through a bridge IP<br />FPGA Design<br />View Data<br />in Real Time<br />A<br />Bridge<br />IP<br /><ul><li> JTAG Bridge IP
  43. 43. SPI Bridge IP
  44. 44. TCP/IP Bridge IP</li></ul>C<br />B<br />D<br />Read/Write Transactions<br />Faster Board Bring-up with Real-TimeSystem Debug<br />
  45. 45. Vision: Target Qsys Applications<br />Qsys can be used in every FPGA design<br />Control plane<br />Reading and writing to control status registers<br />Data plane<br />Data switching (muxing, demuxing), aggregation, bridges<br />
  46. 46. Summary<br />Qsys increases design productivity through automated interconnect generation<br />Faster design cycles<br />Less design errors<br />Easier verification<br />Shorter time to market<br />Qsys new features include:<br />High performance interconnect with pipelinedNetwork-On-Chip architecture<br />Scalable system design with hierarchy support<br />Broad IP portfolio availability with industry-standard interfaces<br />Design re-use with IP management capabilites<br />Faster board bring-up with real-time debug capabilities<br />