Session six

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Session six

  1. 1. http://www.bized.co.uk Session 6Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  2. 2. http://www.bized.co.ukContents -Scrambler mini project discussion -Finite State Machine -What is FSM? -Moore machine 6 -Mealy machine -FSM in VHDL 2 Copyright 2006 – Biz/ed
  3. 3. Session 6 http://www.bized.co.ukScrambler mini project discussion B(i)=[b(i)+c(i)]mod2 3 Copyright 2006 – Biz/ed
  4. 4. Session 6 http://www.bized.co.uk FSM 4 Copyright 2006 – Biz/ed
  5. 5. Session 6 http://www.bized.co.ukWhat is FSM Any digital system consists of two part: Data Part Data part Responsible for the processing of data. The Inputs Outputs processing is done through some blocks such as (full adder, digital filter, decoder,…) Controls Control part Describes how and when these blocks will communicate with each other. The control part is generally described using a finite Control Part state machine. 5 Copyright 2006 – Biz/ed
  6. 6. Session 6 http://www.bized.co.ukWhat is FSM S1Finite State MachineFSM is simply a finite number of states that S3 S2each state describes a certain set of controloutputs that are connected to the data partblocks.The transition between these states dependsmainly on the inputs of the FSM.There are two main types of FSM: S4Moore FSMMealy FSM 6 Copyright 2006 – Biz/ed
  7. 7. Session 6 http://www.bized.co.ukFSM in VHDLAssigning Moore Outputs OutputUse a combinational ‘process’ to model Output Logic LogicOutputs are only dependant on the current stateAssigning Mealy Outputs Outputs = f(State)Use a combinatorial ‘process’ to model Output LogicOutputs are dependant on the current state & the input Outputs = f(Inputs, State) Output Logic 7 Copyright 2006 – Biz/ed
  8. 8. Session 6 http://www.bized.co.ukMoore FSM In a Moore finite state machine, the output of the circuit is dependent only on the state of the machine and not on its inputs.Inputs Next Present state state Outputs Next Machine Output State State Logic Logic Registers 8 Copyright 2006 – Biz/ed
  9. 9. Session 6 http://www.bized.co.ukMealy FSM In a Mealy finite state machine, the output is dependent both on the machine state as well as on the inputs to the FSM.Inputs Next Present state state Outputs Next Machine Output State State Logic Logic Registers 9 Copyright 2006 – Biz/ed
  10. 10. Session 6 http://www.bized.co.ukMoore FSM transition condition 1 state 1 state 2 transition condition 2Mealy FSM transition condition 1 / output 1 state 1 state 2 transition condition 2 / output 2 10 Copyright 2006 – Biz/ed
  11. 11. Session 6 http://www.bized.co.uk• Synchronous & asynchronous FSM -Moore (Synchronous ) -Mealy(asynchronous ) Example 26 11 Copyright 2006 – Biz/ed
  12. 12. Session 6 http://www.bized.co.uk Moore FSM that Recognizes Sequence “10” 0 1 1 0 S0 / 0 S1 / 0 S2 / 1 reset S0: No S1: “1” S2: “10”Meaning elements observed observedof states: of the sequence observed 12 Copyright 2006 – Biz/ed
  13. 13. Session 6 http://www.bized.co.ukMealy FSM that Recognizes Sequence “10” 0/0 1/0 1/0 S0 S1 reset 0/1 S0: No S1: “1” Meaning elements observed of states: of the sequence observed 13 Copyright 2006 – Biz/ed
  14. 14. Session 6 http://www.bized.co.ukclock 0 1 0 0 0input S0 S1 S2 S0 S0Moore S0 S1 S0 S0 S0Mealy 14 Copyright 2006 – Biz/ed
  15. 15. Session 6 http://www.bized.co.uk 3-FSM in VHDL-Finite State Machines Can Be Easily Described With Processes-Synthesis Tools Understand FSM Description if Certain Rules Are Followed-----State transitions should be described in a process sensitive to clock and asynchronousreset signals only-----Output function described using rules for combinational logic, i.e. as concurrentstatements or a process with all inputs in the sensitivity list 15 Copyright 2006 – Biz/ed
  16. 16. Session 6 http://www.bized.co.ukFSM in VHDLThe “3 Processes, 1 Clocked + separate transitions/actions” style1-Process modeling “Next State Logic” Next State Logic2-Process modeling "Current State Registers" State Registers3-Process modeling “Output Logic” Output Logic 16 Copyright 2006 – Biz/ed
  17. 17. Session 6 http://www.bized.co.ukFSM in VHDLNext-State LogicUse a combinational ‘process’ to model next state logicprocess ( current_state, <in1>, <in2>, <in3> … )Begin case ( Current_State ) is when <state1> => Next if ( <condition (<in1>, <in2>...)> ) then State Next_State <= <state2>; Logic elsif ( <condition (<in1>, <in2>...)> ) then Next_State <= <state3>; ...end process; 17 Copyright 2006 – Biz/ed
  18. 18. Session 6 http://www.bized.co.ukFSM in VHDLCurrent-StateUse a sequential ‘process’ to describe current state logic*Process (clock)Begin if rising_edge (clock) then if ( reset = 1 ) then -- synchronous reset Current_State <= <reset_state>; else Current_State <= Next_State; State Registers end if; end if;end process; 18 Copyright 2006 – Biz/ed
  19. 19. Session 6 http://www.bized.co.uk• Vending Machine -Moore -Mealy Example 27 19 Copyright 2006 – Biz/ed
  20. 20. Session 6 http://www.bized.co.ukVending MachineSpecifications-Deliver package of gum after 15 piaster deposited-Single coin slot for 5 and 10 piastersStep 1 : Understand the problem Draw a block diagram 20 Copyright 2006 – Biz/ed
  21. 21. Session 6 http://www.bized.co.ukStep 2 : Draw a state diagram Reset D S0 N S6 S1 D N D N N = 5 piaster S8 S7 S3 S2 D = 10 piaster open open open D N S5 S4 open open 21 Copyright 2006 – Biz/ed
  22. 22. Session 6 http://www.bized.co.ukStep 3 : State Minimization Reset S0 N S1 D N N = 5 piaster D D = 10 piaster S2 N,D S3 open 22 Copyright 2006 – Biz/ed
  23. 23. Session 6 http://www.bized.co.ukStep 4 Write VHDL code (Moore)Inputs and Outputs Reset S0library IEEE; Nuse IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL; S1 Duse IEEE.STD_LOGIC_UNSIGNED.ALL; Nentity vend_machine_moore is D Port (N : in STD_LOGIC; S2 D : in STD_LOGIC; reset : in STD_LOGIC; N,D clk : in STD_LOGIC; S3 tank_open : out STD_LOGIC);end vend_machine_moore; open 23 Copyright 2006 – Biz/ed
  24. 24. Session 6 http://www.bized.co.ukDefine the states ResetWe need to define a new type for the names of the states S0 N S1 Darchitecture Behavioral of vend_machine_moore is Ntype states is (s0,s1,s2,s3); D S2signal n_state,p_state :states;begin N,D S3 open 24 Copyright 2006 – Biz/ed
  25. 25. Session 6 http://www.bized.co.ukThe transition process ResetResponsible for the transition of states from present state to next state. S0 N transition :process(clk,reset) S1 D begin if reset=1 then N p_state <=s0 ; D elsif rising_edge(clk) then S2 p_state <= n_state ; end if; N,D end process transition; S3 open 25 Copyright 2006 – Biz/ed
  26. 26. Session 6 http://www.bized.co.ukNext State logic processResponsible for generating the next state logic. Resetnext_state :process(N,D,p_state)--p_state in list to trigger process if ips are constants S0begin case p_state is N when s0 => when s2 => if N=1 then if N=1 then S1 D n_state <= s1; n_state <= s3; elsif D=1 then elsif D=1 then n_state <= s2; n_state <= s3; N else n_state <= s0; else n_state <= s2; D S2 end if; end if;when s1 => when s3 => N,D if N=1 then n_state <= s0; n_state <= s2; -------------- S3 elsif D=1 then end case; n_state <= s3; else n_state <= s1; end process next_state; open end if; 26 Copyright 2006 – Biz/ed
  27. 27. Session 6 http://www.bized.co.ukOutput logic processResponsible for generating the output logic. Resetoutput_logic :process(p_state) S0begin case p_state is N when s0 => tank_open <=0; S1 when s1 => tank_open <=0; D when s2 => tank_open <=0; when s3 => tank_open <=1; N end case; D S2end process output_logic ; N,Dend Behavioral; S3 open 27 Copyright 2006 – Biz/ed
  28. 28. Session 6 http://www.bized.co.ukStep 4 Write VHDL code (Mealy) ResetNote : the number of states in Mealy FSM 3 !!library IEEE; S0use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; N, 0entity vend_machine_moore is N/D, 1 D, 1 S1 D, 0 Port (N : in STD_LOGIC; D : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; N, 0 tank_open : out STD_LOGIC);end vend_machine_moore; S2architecture Behavioral of vend_machine_mealy istype states is (s0,s1,s2);signal n_state,p_state :states;begin 28 Copyright 2006 – Biz/ed
  29. 29. Session 6 http://www.bized.co.uktransition :process(reset,clk)begin if clr=1 then p_state <=s0 ; elsif rising_edge(clk) then p_state <= n_state ; end if;end process transition;next_state :process(N,D,p_state)begin case p_state is when s0 => if N=1 then tank_open <=0; n_state <= s1; elsif D=1 then n_state <= s2; tank_open <=0; else n_state <= s0; tank_open <=0; end if; 29 Copyright 2006 – Biz/ed
  30. 30. Session 6 http://www.bized.co.ukwhen s1 => if N=1 then n_state <= s2; tank_open <=0; elsif D=1 then n_state <= s0; tank_open <=1; else n_state <= s1; tank_open <=0; end if; when s2 => if N=1 then n_state <= s0; tank_open <=1; elsif D=1 then n_state <= s0; tank_open <=1; else n_state <= s2; tank_open <=0; end if;end case;end process next_state;end Behavioral; 30 Copyright 2006 – Biz/ed
  31. 31. Session 6 http://www.bized.co.uk• Gumball Vending Machine lab 12 31 Copyright 2006 – Biz/ed
  32. 32. Session 6 http://www.bized.co.uk• String Detector to detect input sequence (1110) draw state diagram (Mealy and Moore) Exercise 6 32 Copyright 2006 – Biz/ed
  33. 33. Session 6 http://www.bized.co.uk• String Detector to detect input sequence (1110) Moore or Mealy lab 13 33 Copyright 2006 – Biz/ed
  34. 34. Session 6 http://www.bized.co.ukQuestions Session-6 34 Copyright 2006 – Biz/ed
  35. 35. Session 6 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 35 Copyright 2006 – Biz/ed
  36. 36. Session 6 http://www.bized.co.ukSee You Next Session 36 Copyright 2006 – Biz/ed

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