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3 d ic

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3 d ic

  1. 1. 3D IC 設計簡介 STC/ITRI 特助 半導體產業推動辦公室 副主任 唐經洲 120090612 成大CAD
  2. 2. Outline More than Moore Process of 3D IC Advantages of 3D IC 2
  3. 3. Moore 咒 (1965)Relative Manufacturing cost per Computer Number of Computer per Integrated Circuit 3 2008/04 in Golden Moore’s Office
  4. 4. Moore’s 1st and 2nd Law Moore’s First Law Chip Density will double ever 18months. This means that memory sizes, processor power, etc. all follow the same curve. Moore’s Second Law The cost of building chip fabrication plants will continue to increase (and the return on investment to decrease) until it becomes fiscally untenable to build new plants. i.e. while it may be technologically possible to continue to double the density of chips every 18 months, the cost of achieving this goal will eventually surpass the profit. 4www.ucd.ie/mecheng/ams/S%20Daniels%20Recent%20advances%202.pdf
  5. 5. Moore’s Law on Microprocessor Duo core Itanium 1.7 B Trs. Pentium 4864004 5
  6. 6. 2003-2008年台灣IC設計業各項重要指標 (1/2) 2003 2004 2005 2006 2007 2008 廠商家數 250 260 268 267 272 275 營業額(億元新台幣) 1,902 2,608 2,850 3,234 3,997 3,749 成長率 28.7% 37.1% 9.3% 13.5% 23.6% -6.2% 內銷比例 45% 37% 34% 34% 33% 39% 資本支出/營業額 3.5% 2.5% 3.0% 3.2% 3.3% 3.1% R&D/營業額 12.8% 9.1% 10.0% 10.8% 11.2% 11.5% 營業額 成長率 5,000 40.00% 4,000 30.00% 3,000 20.00% 2,000 1,000 10.00% 0 0.00% 2002 2004 2006 2008 2010 2002 2004 2006 2008 2010 -10.00% 6
  7. 7. 2003-2008年台灣IC設計業各項重要指標 (2/2) 2003 2004 2005 2006 2007 2008 毛利率 37.0% 34.6% 36.0% 37.0% 37.3% 36.9% 營業利益率 21.4% 19.0% 20.1% 20.6% 20.8% 20.7% 稅後淨利率 20.4% 15.0% 16.3% 16.8% 17.1% 16.9% 平均員工產值 1,514 1,242 1,124 916 1,132 1,116 (萬/新台幣)1999~2007年各主要貨幣兌美元走勢圖 7 (年)
  8. 8. More than Moore 3D ICIC ?? More Money – – 3D ?? 820090612 成大CAD
  9. 9. Skyscrapers Location : Dubai Location : Taiwan Location : Malaysia Height : 705 Meters Height : 508 M Height : 452 Meters Floors : 160 Floors : 101 Floors : 88 9 To Be Completed : 2008 Built : 2004 Built : 1998
  10. 10. More Than Moore: 3D IC 3-D Integrated Planar (2-D) Integrated Circuits Solid State Discrete Circuits Transistors Heterogeneous Integration 19471950s 1960s 1958 1970s 1980s 1990s 2000s 2000s 2010s 2020s 1950s 2000s 2010s 2020s >>1B transistors Source: Fairchild, Intel 10 & CS Tan(NTU-SG)
  11. 11. 2D vs. 3D 20顆晶片 堆疊(TSV) 11 http://www.jonathassociates.com/AJA/droppedImage.png
  12. 12. 2D vs. 3D 12
  13. 13. 3D Integration 13
  14. 14. Why Not SOC ? 投資成本 (Cost) 負擔太高 材料 (Material) 發展不易 微影技術 (Lithography) 太過困難 3D 電晶體架構 (Transistor Architecture) 尚未成熟 製程變異性(Variability) 難以掌握 散熱問題 (Thermal Dissipation)影響深遠 14
  15. 15. 投資成本 (Cost) 負擔太高(1/2) SOC 早在 2003 年的 ISSCC 已經被 Intel 的一 位Architecture 主管 Jay Heeb宣告``死刑‘’了 15
  16. 16. 投資成本 (Cost) 負擔太高(2/2) 16
  17. 17. 材料 (Material) 發展不易 (1/2) 17
  18. 18. 材料 (Material) 發展不易 (2/2) 1990~2000 2000~2005 2005~2010 Glass (oxide) Glass (oxide) Glass (oxide) Tungsten Tungsten Tungsten Copper Copper Shallow Trench Shallow Trench Polysilicon Polysilicon Low K Cap Ultra Low k Metal Gates Gate Insulators High k Dielectrics Ir & Pt Electrodes Magnetics 18
  19. 19. Delay in Low-k Implementation 19
  20. 20. 微影技術 (Lithography) 太過困難 (1/2) 45nm Lithography Lithography Layout pattern Layout pattern 65nm dependence dependence90nm Lithography Lithography Immersion litho, Immersion litho, Back-end integration Back-end integration OPC/PSM integr. w/ OPC/PSM integr. w/ OPC/PSM integration OPC/PSM integration Low-k Low-k photo-window photo-window w/ photo window w/ photo window CMP CMP Front-end/Transistor Front-end/Transistor Front end/Transistor Front end/Transistor Product ramp issues Product ramp issues Layout dependent Layout dependent New gate/oxide New gate/oxide Yield vs. Yield vs. performance performance architectures architectures performance performance Parametric variation Parametric variation Reliability Reliability 20
  21. 21. 微影技術 (Lithography) 太過困難 (2/2) Layout 0.25µ 0.18µ 0.13µ 90-nm 65-nm 21
  22. 22. 3D 電晶體架構 (TransistorArchitecture) 尚未成熟 22
  23. 23. 製程變異性(Variability) 難以掌握 23
  24. 24. 散熱問題 (Thermal Dissipation)影響深遠 (1/2) IBM 24
  25. 25. 散熱問題 (Thermal Dissipation)影響深遠 (2/2) Intel 25
  26. 26. Via First Process 26
  27. 27. Via Last Process Laser drilling Wet Etching Plasma (DRIE) Etching 27
  28. 28. Aspect Ratio 28
  29. 29. FSI (Front Side Illumination) vs. BSI 29
  30. 30. SoC vs. SiP vs. 3D IC 之比較 SOC SIP 3DICForm Factor Δ Δ √Density Δ Δ √Performance (speed, Δ X √frequency, power)Signal process packing Δ X √densityManufacturing cost in high Δ X √quantitiesHeterogeneous integration X √ ΔManufacturing cost in √ Δ Xlow/medium quantitiesManufacturing ready (2007) Δ √ X √: Best, Δ: Medium, X: Worst 30
  31. 31. 用3D-IC 技術來設計的好處 (1/2) 提高連線密度 (Improve Interconnect Density) 減小外觀尺寸(Reduce Form Factor) 減少雜散電容與電感 (Reduce Parasitic Capacitance/Inductance) 提高速度(Increase Speed) 降低功耗(Reduce Power Consumption) 減低生產費用(Reduce Cost) 提供異質整合 (Provide Heterogeneous Integration) 改善可靠度 (Improve Reliability) 31
  32. 32. 用3D-IC 技術來設計的好處 (2/2) 減少 ESD 需求 (Reduce ESD Requirement) 提高散熱效果 (Improve Heat Dissipation) 提高良率 (Increase Yield) 提高資料安全性 (Improve Data Security) 可延展性/可規畫性/可替換性 (Scalable/Reconfigurable/Replaceable) 簡易的互連體(Simple Interposer) 32
  33. 33. Technical Barriers -- Design EDA Tools Front-end Back-end Multi-Process Application 33
  34. 34. Technical Barriers -- Thermal Thermally aware P&R Cooling Thermal vias Micro-fluid 34
  35. 35. Technical Barriers -- Test KGD (Known Good Die) Yield 35
  36. 36. Major Applications of 3D IC 影像感測器(CMOS Image Sensors) 記憶體(Memories) SRAM/DRAM NAND 處理器(Processor) 感測器與 DSP (Sensor and DSP) 現場可規劃邏輯陣列 (FPGA) 微機電系統 (MEMS) 36
  37. 37. 3D IC Application Forecast 37
  38. 38. 不同公司對於3D-IC 市場之預估預估者 註iSuppli 到2010 年三維晶片市場約有 33 億美金iSuppli 到2014 年三維晶片市場總值約有 173 億美金Prismark 到2006 年互連市場的總值 約有 340 億美金Prismark 到2010 年14億顆3D 封裝形式的 IC Yole 到2010 年10 億顆Flash Memory 會用 TSV 堆疊技術 Yole 到2015 年,測試 (Test) ,電子設計自動化工具 (EDA),與熱管理(Thermal Management),到了 2011 年這些工具都不會成熟 Yole 到2015 年25% 的記憶體會由 3D-TSV 所設計 Yole 到2015 年6% 的IC (不含記憶體) 會由 3D-TSV 所設計 ITIS 應用3D IC 之 SSD渴望在 2010~2012 大幅成長EMC-3D 2007年3D-LSI的加工成本約為410美元,預估到2008年降為約241美元,到2009 年則降為約162美元,已經在200美元之下,下降程度為現在成本的約60%以上 NXP 2012 年3D IC 就會真實呈現在市場上,其推動力量為 Cost, performance, 及 Form factor. 2008 3D-IC t產能為 45000 Wafer, 到了 2014 會有4 百萬片 Aviza 2007: 未來5~10 年會有50% 的晶片是由 TSV 技術所製造Advanced 2008 年TSV 市場開始, 2009 年Flash Memory可以量產,2010 年3D SRAM 與Package DRAM 市場開始 38
  39. 39. 3D IC 廠商產品佈局概況廠商型態 廠商名稱 主要應用產品及進度 Elpida 工業及消費性 DRAM (Prototype) Freescale 工業 RF (Prototype), 消費性 MEMS (R&D) Hynix 工業及消費性 Flash 及 DRAM (Prototype) IBM RF (Prototype), CIS (R&D) Intel Logic (R&D) Micron Flash, DRAM (Prototype), 汽車用 CIS (Production) IDM NEC DRAM (Prototype) NXP RF (Production), 消費性 MEMS (R&D) Renesas Logic (R&D) Samsung 通訊 CIS (Prototype), Flash, DRAM (Prototype) Sharp CIS (Prototype), Logic (R&D) Sony Logic (R&D) STM RF (Production), CIS (Production),MEMS (R&D) Chartered DRAM (Production), Logic (Prototype) Foundry TSMC CIS, MEMS (R&D) Amkor Flash, DRAM (Prototype) Packaging ASE RF (Prototype), DRAM, Flash (Prototype) Xintec CIS (Production) 39
  40. 40. 3D IC Example: Samsung Samsung 16Gb NAND stack with TSVhttp://www.techpowerup.com/10837/Samsung_Develops_3D_Memory_Package.html 40
  41. 41. 3D IC Example: IMEC 41
  42. 42. Intel 80 cores 3D IC structure 42
  43. 43. 歐盟 e-Cube 德積 /MuChip… 雷凌/RaLink… 聯發科/MediaTek 盛群/Holtek, 義隆/ELAN… 原相/PixArt… 力錡/Richtek… 學術界 (台清交成…) 將環境變化轉化為電力 43
  44. 44. 3D IC EDA Tool: R3 Logic 44
  45. 45. 3D EDA Tool: Cadence 45
  46. 46. 2 ½ D or 3D ? Intel 45nm Systems-in-a-Cube (Source: IMEC)http://www.solid-state.com/articles/article_display.html?id=224942 46
  47. 47. Effort Needed for Manufacutrable 3D 47
  48. 48. Technical Challenges for 3D IC 48
  49. 49. Business Challenge for 3D IC 49
  50. 50. More Closed Link on 3D IC ?? IC設計 光罩製作 IC製造 威盛 中華凸版電子 矽統 台積電 揚智 世界先進 IC封裝測試 台灣光罩 聯電 凌陽 瑞昱 旺宏 日月光 義隆 翔準先進光罩 茂矽 福雷電 松翰 茂德 矽品 偉詮 華邦 華泰 民生 力晶 菱生 太欣 南亞科技 華特 通泰 漢磊 立衛 晶圓生產 晶磊 立生 泰林 鈺創 崇越 超豐 矽成 中美矽晶 台晶 漢磊 導線架 博達 順德 旭龍 測試設備 佳茂 化學品 訊利 台銷 (硝酸) 金線 永光 (光阻劑) 致茂 長興 (CMP劑) 50
  51. 51. 加量不加價 ? 51
  52. 52. 新的3D 定義 altitu D e D ocument rea D ing 52
  53. 53. Thanks for Your Attention 53

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