Managing IP Subsystems at the System Level


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Semico Research estimates that over 50 IP cores are present on average in SoCs being developed today. As a result, more SoCs contain distributed computing, multicore architectures. These topologies are making it increasingly difficult to manage power, security, error-recovery and even boot sequencing. No one IP core can easily be given enough accessibility and control to manage the other cores without complicating the architecture. And with many software operating systems and applications on the single SoC, synchronizing their states with their support hardware is also becoming complex.

Solutions designed in-house often result in adding some combination of extra logic and additional software development to manage the system tasks. These solutions are often designed and tested specifically for the SoC configuration. As complexities grow, significant cost and verification risks are now escalating from the need to redesign and re-verify these solutions for each new chip development project.

SSM represents a unique “subsystem” alternative which decouples the system management from the specific design, promoting high reuse and faster hardware-software integration. SSM creates virtualization in the SoC architecture.

Hardware level virtualization comes from SSM’s ability to operate as a self contained unit independent from the other SoC components. SSM connects to the other IP cores using a simple hardware bus scheme. SSM utilizes commands sent to it by any source to execute the necessary signal level transitions that change an IP cores’ operation state. Software virtualization comes from SSMs ability to synchronize software and hardware states as it is performing the hardware level tasks. SSM provides API’s and a kernel which is hosted on SSMs hardware core. Drivers are connected to other software on the SoC, which communicates the status of the hardware state changes. SSM can also take command directives directly from the software through the drivers.

Says Rich Wawryzniak, Senior Analyst, Semico Research, “Virtualizing system management using a subsystem approach creates real economies when measuring the development costs for complex SoCs. Since these costs are multiplying from both hardware and software complexity growth, the need for modular SoC architectures that effects both hardware and software development dictates the need for these subsystems.”

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Managing IP Subsystems at the System Level

  1. 1. SoC System Manager (SSM) The Industry’s First SoC IP Subsystem Dedicated To System Resource Management Co-Developed By: 1
  2. 2. SoC Complexity Accelerating "Average" Number of IP Blocks on SoCs Today Source: Semico Research 100 90 Avg. Number of SIP Blocks 80 70 Over 50 IP Blocks! 60 50 40 30 20 10 0 2002 2003 2004 2005 2006 2007 2008 2001 2000 1998 1999 2009* 2010* 2013* 2011* 2012* Avg. Number of CPU / DSP / Controllers Avg. Number of 'Other' SIP Blocks Avg. Number of Embedded Memory Blocks Total SIP Blocks Volume Consumer Markets Driving the Trend 2
  3. 3. The Resource Management Challenge Host Multimedia Comm Lack of directmanager Subsystem hardware allows SoC architecture to connectivity & complex Subsystem Subsystem Subsystem use a control plane interconnect arbitration complicates that provides framework ability for host independent top down to manage system state changesmanagement H/W- system and maintain with Global Interconnect H/W-S/W synchronization S/W synchronization during during operation and error operation and error recovery recovery System I/O Memory Manager Subsystem Subsystem Subsystem How Will the System Be Managed? Host Visibility and ControlControl Plane aOptimize System Management Virtualization Based on Inadequate to More Effective Architecture 3
  4. 4. Introducing SSM: System Resource Management IP CPU DSP Hardware/Software IP “block” SSM SSM H/W CTL MEM CPU I/O CTL SSM Consolidates and Virtualizes these System Management Services: • Power and Security Management • Error Recovery • Boot and Reset Sequencing SSM Connects Directly to Hardware AND Synchronizes with Software via Drivers 4
  5. 5. SSM Advantages  Lowers development costs and risks  Design and verify at architecture stage  Pre-verify system management policies and reuse  Increases the value of the SoC deliverable  Improves software-system management control  Mitigates hardware-software dependencies  Creates new opportunities to innovate  New power management schemes made possible  Increasing integration complexities manageable Shift System Management Out of the Design and into the Architecture 5
  6. 6. The “Ripple Savings” Effect  Architecture  Top down system management provides high reuse framework for streamlining product line management.  Design  Pre-defined topology eliminates creating ad hoc solutions during the design process.  Verification  Test schemes predesigned during architecture development accelerates starting point for verification script generation.  Software Development  Shift to architecture significantly reduces burden to create similar solutions and provides more chip behavior predictability before chip design commences.  Bring Up and Test  Provides unique post silicon control of IP cores for checkout and functional verification. Scripts also a way to implement potential work-arounds.  Production Engineering  Consistent testing methodology throughout all phases of the development cycle yields a comprehensive suite of testing sequences that are also easily modified. Savings Multiply During Development
  7. 7. Quantifying the Aggregate Savings (Assumes $3.25M USD, 300 P-M Project Cost Before SSM) 10 9 8 Before SSM Possible Project Savings CAPITAL (M$ USD) 7 Advance Tech Marketing Production Curves 6 After SSM 33% Capital Reduction AND 5 10% Labor Reduction 4 OR A 42% Labor Reduction for 3 Same Capital Investment 2 B 1 0 100 200 300 400 500 600 700 800 900 LABOR (PERSON - MONTHS) Reference: Semico Research SoC Reports 7
  8. 8. SSM Use Models 8
  9. 9. SSM Use Models  SSM facilitates the management of system resources such as power management, security, error recover, and boot and reset sequencing  Control of these system resources, and the ability to communicate directly with software, makes SSM an excellent resource for many different uses:  Hardware Development ○ Architecture Enhancement  Top down system management provides high reuse framework for streamlining system resource management across product lines ○ Design Acceleration  Pre-defined topology within the architecture eliminates creating ad hoc solutions during the design process. ○ Verification  Test schemes predesigned during architecture development can be used to accelerate the starting point for verification test generation.
  10. 10. SSM Use Models… continued  Software Development  Shift to architecture significantly reduces burden to create similar system management solutions in software and creates clear methodology for maintaining synchronization between software and underlying IP hardware during operation  Bring Up and Test  Provides unique post silicon control of IP cores for debugging. Scripts also a way to implement potential work-arounds to problems associated with IP block state changes.  Production Engineering Testing  Consistent testing methodology throughout all phases of the development cycle yields a comprehensive suite of testing sequences that are also easily modified.  Remote Diagnostics and Updating  SSM can deliver IP block state data to a remote host using a communications link or a JTAG port for debugging and monitoring functions.  SSM can be used to coordinate firmware and software updates remotely through the use of its communications bus and connectivity to the IP blocks. 
  11. 11. SSM Technical Overview 11
  12. 12. SSM Hardware Connectivity SSM register blocks and control bus CPU DSP SSM SSM CTL H/W MEM CPU I/O CTL • SSM H/W block contains processor which executes commands • An SSM block is connected to each IP block to be managed • SSM executes requests through SSM registers/bus • Message passing option which is user defined 12
  13. 13. SSM Connects to Software via Drivers Application Software •Applications or O/S Communicates O/S with SSM via API’s and Drivers API SSM Software •SSM Software Translates SSM Commands to Signals SSM Hardware •SSM Hardware Executes State SoC Hardware Transitions Conditional or Unconditional Command Execution 13
  14. 14. “Top Down” Power Management Simple IPTV Example SSM Scripts Accept IPTV Packets CPU HOST ON OFF DSP ON OFF Process Macroblocks SSM H/W Power Sequencing MEM Managed by SSM OFF CPU ON I/O CTL Software Synchronization Managed by SSM IP Packets Macroblocks 14
  15. 15. SSM Facilitates Policies  Policies (chains of commands) accepted from any source are loaded into local RAM  Executes policy enforcement in any desired pattern (called scripting)  Guaranteed conditional or unconditional enforcement sequencing  Hardware uses message passing for IP block to block communication  Software uses drivers Sequences of Commands Are Predetermined and Tested For Any Number of Scenarios 15
  16. 16. Virtualizing System Management  Typical Multicore Host Reset Script  Suspend DSP; Send message to DSP O/S on DSP, Wait for ACK, toggle IP core enable signal inactive  Suspend MPE; Same as above  Reset Host; Send message to host O/S, wait for ACK, toggle reset  Resume DSP; Activate enable signal, send message to DSP O/S  Resume MPE; Same as above Software Scripts are Developed Independent of Hardware Development 16
  17. 17. SSM Advantages  Simplifies accessibility and control of all managed IP blocks  Guaranteed synchronization between hardware and software while executing complex sequences  Virtualization of system management functions  Compartmentalizes instantiation dependencies  Improves software’s ability to control hardware Saves Time and Money Offers SoC Architecture Consistency 17
  18. 18. SSM Subsystem Components  Hardware (Soft IP)  SSM Controller  SSM Register bus connection  Software  SSM software  API  Drivers 18
  19. 19. SSM Addresses Key System Issues  Standardizes Management of Key System Functions  Power, security, error recovery, boot sequencing  Eases Hardware Software Integration  Provides A Reusable Architecture Across Many SoCs A Subsystem Suited for Universal Adoption 19
  20. 20. About ChipStart  ChipStart is the only, full-function semiconductor IP solution alternative  IP Subsystem Solutions oriented  Experienced team (+250 years in IP)  Delivering value with integration ChipStart LLC - CONFIDENTIAL
  21. 21. ChipStart Contact Page ChipStart LLC Northeast USA 228 Hamilton Ave., 3rd Floor Cambridge, MA 02140 Palo Alto, CA 94301 Office: +1.617.678.9814 Office: +1.650.461.9195 Email: Central USA ChipStart UK Austin, TX 78726 Maidenhead, Berkshire SL6 4LZ Office: +1.512.560.4672 Office: +44 20 3286 0905 Northwest USA ChipStart France Evergreen, CO 80439 91570 Bievres Office: +1. 303.506.1088 Office: +33-682-652-808 ChipStart Canada ChipStart Israel Oakville, ON L6J 0A2 Raanana, 43380 Office: +1.905.634.6688 Office: +972 9 7713312 Fax: +1.905.592.2048 ChipStart Japan ChipStart China Level 28, Shinagawa Intercity Tower A Unit A, 14F, Asia Harvest Commercial Centre 2-15-1 Konan, Minato-ku Shau Kei Wan, Hong Kong Tokyo 108-6028 Office: +86 138 2336 5688 Office: +81-3-45789359 FAX: +81-3- 6717-4141