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Very little workshop on HLS:
Mention of Synthesizing hardware using high level language, in particular C-like languages. Analysis of existent old language since 1980 to 2000: Cones, HardwareC, Transmogrifier C, SystemC, C2Verilog, Handel-C. Open problems using C-like languages (taken from Stephen Edwards' "The challenges of synthesizing Hardware from C-like languages").
Hardware design and synthesis using Esterel, reactive and synchronous language, ideal to describe a *behavioural* structure of hardware concurrent real-time controller and to test formal correctness. Easiness in creation of VHDL, Verilog, SystemC, Finite State Automata, dataflow design, and implementation on ASIC or FPGA or RePIC (processor architecture supporting direct esterel execution).
Example of a Preudo-Random Bit Sequence using Esterel versus the implementation using OrCAD software