INTRODUCTION The Core 2 brand refers to Intels family of 64-bit dual- core microprocessors (CPUs) of the eighth-generation Core architecture This is evolved from the 32-bit Yonah mobile processor. The Yonah comprised of two interconnected Pentium Ms packaged, as a single die (piece) silicon chip . In the case of multi core processor, the entire chip has multi independent computer processors that can work together to increase total computer performance.
CORE 2 BRANDS DUO (Dual Core) QUAD (Four Core) EXTREME (Dual- or Quad-core CPUs with higher speeds)
CONROEThe first Intel Core 2 Duo processor cores, code-named Conroe .It provides 40% more performance at 40% less power compared to the Pentium DThey are manufactured with 4 MiB L2 cache , with only 2 MiB of usable L2 cache, Other 2MiB cache disabled.
CONROE XE Conroe XE has a clock speed of 2.93 GHz It has an FSB of 1333 MT/s ,Where as conroe has an FSB of 1066 MT/s. The TDP for this family is 75–80 watts. At full load the X6800 does not exceed 45 °C The only major difference between the regular Core 2 Duo and Core 2 Extreme is
ALLENDALE The Allendale core, manufactured with 2 MiB L2 cache in total, offers a smaller die size and therefore greater yields. FSB Ratings Conroe core 1066MT/s. Allendale core 800MT/s. Example for Allendale is Core 2 Duo E4000 series and they are cheaper.
KENTSFIELD This is a quad core CPU branded as Core 2 Quad The max. power consumption (TDP) of the Kensfield is 135 watts, QX6700 - 110 W, Q6600 - 105 W the QX6700 consisted of two E6700 chips connected together by a 1066 MT/s FSB . The Kentsfield is one socket processor sitting in a LGA775 socket, as the Core 2 Duo does
TERMINOLOGIES Clock Speed : The speed at which the processor executes instructions. Every processor contains an internal clock that regulates the rate at which instructions are executed. For eg . 3GHz Front Side Bus Speed :The speed of the bus that connects the processor to main memory (RAM). As processors have become faster and faster, the system bus has become one of the chief bottlenecks in modern PCs. Typical bus speeds are 400 MHz, 533 MHz, 667 MHz, and 800 MHz.
CACHE The purpose of a cache is to enable the CPU to access recently used information very quickly. Some caches are bigger than others. A typical L1 cache is 256Kb and a typical L2 cache is 1MB. L1 cache is typically smaller and faster than L2 cache. L2 Cache is ultra-fast memory that buffers information being transferred between the processor and the slower RAM L3 Cache is larger than L2..Integrated Level 3 cache provides a faster path to large data sets stored in cache on the processor. This results in reduced average memory latency and increased throughput
MORE Package : The physical packaging or form factor in which the processor is manufactured. These factors like size, shape, number and layout of the pins or contacts determines the package. Eg LGA775 Hyper-Threading: This technology is a technique which enables a single CPU to act like multiple CPUs. A CPU is made up of many smaller components. At any given time, one of these components might be busy, while the other components are waiting to be utilized. Hyper-Threading enables different parts of the CPU to work on different tasks concurrently. In this way, a CPU with Hyper-Threading appears to be more than one CPU.
OVERCLOCKING AND MOTHERBOARD Overclocking is the process making a computer component run at a higher speed than that specified by the manufacturer. The CPU clock speed is the product of the FSB speed and the CPUs multiplier The motherboard is the most essential component in a personal computer .It is the piece of hardware which contains the computers micro-processing chip and everything attached to it is vital to making the computer run.
MOORE’S LAW In 1965, Intel co-founder Gordon Moore saw the future. His prediction, now popularly known as Moores Law, It states that the number of transistors on a chip doubles about every two years. This observation about silicon integration, made a reality by Intel, the worlds largest silicon supplier, has fueled the worldwide technology revolution.
INTEL’S MICRO ARCHITECTURE This is the architecture used in core 2 processors It is the size and spacing of the processors transistors , which partially determine the switching speed. The diameter of transistors is measured in nm .eg.65 nm technology Processor architecture maintains instruction set compatibility so processors will run code written for processor generations, past, present, and future. Microarchitecture refers to the implementation of processor architecture in silicon.
ENHANCEMENT OF ARCHITECTURE The architecture can be enhanced by the following features INTEL WIDE DYNAMIC EXECUTION ADVANCED SMART CACHE SMART MEMORY ACCESS 65 NANO TECH
INTEL WIDE DYNAMIC EXECUTION One such feature for reducing execution time is macrofusion In Netburst architecture ,each incoming instruction was individually decoded and executed Macrofusion enables common instruction pairs to be combined into a single internal instruction (micro-op) during decoding Two program instructions can then be executed as one micro- op, reducing the overall amount of work the processor has to do.
Micro-op fusion “fuses” micro-ops derived from the same macro-op to reduce the number of micro-ops that need to be executedReduction in the number of micro-ops results in more efficient scheduling and better performance at lower power. By doing more in less time, macrofusion improves overall performance and energy efficiency.
ADVANCED SMART CACHE:The Intel Advanced Smart Cache is a multi-core optimized cache that improves performance and efficiencyTo accomplish this, Intel shares L2 cache between cores.To understand the advantage of this design, consider other current multi-core implementations don’t share L2 cache among execution cores.
With Intel’s shared L2 cache, the data only has to be stored in one place that each core can accessBy this smart cache also allows each core to dynamically utilize up to 100 percent of available L2 cacheMulti-Core Optimized Cache also enables obtaining data from cache at higher throughput rates
SMART MEMORY ACCESS SMA involves prefetchers and the memory disambiguation result in improved execution throughput by hiding latency to the memory subsystem. Intel Smart Memory Access includes an important new capability called memory disambiguation which increases the efficiency of processor by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute
Prefetchers do just that—“prefetch” memory contents before they are requested so they can be placed in cache and then readily accessed when needed the Intel Core microarchitecture uses two prefetchers per L1 cache and two prefetchers per L2 cache. These prefetchers detect multiple streaming and strided access patterns simultaneously L1 cache : “just-in-time execution L2 cache : holds the data the cores may need in the future.
65 nm TECHNOLOGY Intels 65nm technology roughly doubles transistor density compared to the previous generation, and delivers industry-leading performance and performance efficiency to innovative technologies such as virtualization and security enhancements that provide the foundation for energy-efficient, feature rich computing solutions.
65nm transistor technologies include: Second generation strained silicon with 10-15 percent improved drive current (over the 90nm process) for improved performance 1.2nm gate oxide and 35nm gates for improved performance NiSi for low resistance cap on gates and source-drains Lower interconnect capacitance through low-k carbon doped oxide dielectric and 0.7x line length scaling, providing increased performance and lower power