Using MDE for the Formal
   Verification of Embedded
   Systems Modeled by UML
     Sequence Diagrams


         Francisco...
Motivation

    To cope with the growing complexity
    of embedded systems design

    Higher levels of abstraction

 ...
Summary
•   Model Driven Engineering (MDE)
•   MDE-based Formal Verification
•   Internal Application Metamodel – IAM
•   ...
Model Driven Engineering
•   Main artifacts to be constructed and
    maintained are models
•   Languages used to express ...
MDE-based Formal Verification
UML model
• Class diagrams (CD)
    –   Application components
    –   Hierarchy and modularity
    –   Structure
• Sequen...
Example: UML model
• UML model: class diagram
Example: UML model
• UML model: main sequence diagram
Example: UML model
• UML model: sequence diagrams
Example: UML model
• UML model: sequence diagrams
Example: UML model
• UML model: sequence diagrams
Internal Application Metamodel
• Structure
Example
• Internal
  Application
  Model
Internal Application Metamodel
• Behavior
Example
• Internal
  Application
  Model
Example: InteractionGraphs
• Internal
  Application
  Model
Internal Application Metamodel
• Labeled Timed Automata
Example
• Internal
  Application
  Model
Transforming UML into IAM+LTA

• Set of transformations between models
  implemented using Xtend language
  from openArchi...
Model Checking using UPPAAL
Future Work
•   Automatic generation of properties
    to be proved by model checking
•   Integration with diferent co-des...
Conclusions
•   Transformation between models is
    used to generate an internal
    representation model
•   IAM+LTA is ...
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Using MDE for the Formal Verification of Embedded Systems Modeled by UML Sequence Diagrams

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Using MDE for the Formal Verification of Embedded Systems Modeled by UML Sequence Diagrams

  1. 1. Using MDE for the Formal Verification of Embedded Systems Modeled by UML Sequence Diagrams Francisco A. M. Nascimento Marcio F. S. Oliveira Flávio R. Wagner SBCCI 2009 Natal, RN
  2. 2. Motivation  To cope with the growing complexity of embedded systems design  Higher levels of abstraction  Exhaustive test of all possible system executions is an impractical or even impossible task • Formal verification methods and tools as a promising approach
  3. 3. Summary • Model Driven Engineering (MDE) • MDE-based Formal Verification • Internal Application Metamodel – IAM • LTA Metamodel - LTA • Transforming UML into IAM+LTA • Case Study • Conclusion and Future Work
  4. 4. Model Driven Engineering • Main artifacts to be constructed and maintained are models • Languages used to express models are defined by means of meta- models • Software development consists of transforming a model into another one until a final model is obtained that is ready to be executed
  5. 5. MDE-based Formal Verification
  6. 6. UML model • Class diagrams (CD) – Application components – Hierarchy and modularity – Structure • Sequence diagrams (SD) – Possible executions of the application – A root SD specifies how the executions are composed – Behavior
  7. 7. Example: UML model • UML model: class diagram
  8. 8. Example: UML model • UML model: main sequence diagram
  9. 9. Example: UML model • UML model: sequence diagrams
  10. 10. Example: UML model • UML model: sequence diagrams
  11. 11. Example: UML model • UML model: sequence diagrams
  12. 12. Internal Application Metamodel • Structure
  13. 13. Example • Internal Application Model
  14. 14. Internal Application Metamodel • Behavior
  15. 15. Example • Internal Application Model
  16. 16. Example: InteractionGraphs • Internal Application Model
  17. 17. Internal Application Metamodel • Labeled Timed Automata
  18. 18. Example • Internal Application Model
  19. 19. Transforming UML into IAM+LTA • Set of transformations between models implemented using Xtend language from openArchitectureWare framework • Xtext language for IAM+LTA parser/editor implementation • Xpand language used to generate textual input for Uppaal • Eclipse Modeling Framework – EMF
  20. 20. Model Checking using UPPAAL
  21. 21. Future Work • Automatic generation of properties to be proved by model checking • Integration with diferent co-design and co-synthesis tools • More experiments to explore the effectivity of the methodology
  22. 22. Conclusions • Transformation between models is used to generate an internal representation model • IAM+LTA is adequate to be used by formal verification – behavior and structure – control/data flow of execution – timed automata model

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